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[U-Boot,v5,07/34] sunxi: clock: Fix OHCI clock gating for H3/H5

Message ID 20180421121945.12864-8-jagan@amarulasolutions.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series phy: sunxi: Add Allwinner sun4i USB PHY | expand

Commit Message

Jagan Teki April 21, 2018, 12:19 p.m. UTC 
From: Chen-Yu Tsai <wens@csie.org>

Clock gating bits on H43/H5 were wrong, fix them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

Comments

Maxime Ripard April 23, 2018, 7:55 a.m. UTC | #1 
On Sat, Apr 21, 2018 at 05:49:18PM +0530, Jagan Teki wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> Clock gating bits on H43/H5 were wrong, fix them.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

You need to have your SoB here.

Maxime
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index c5dea45985..6fa6cf40ee 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -351,13 +351,10 @@  struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
 #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
 #ifdef CONFIG_MACH_SUNXI_H3_H5
-/*
- * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
- * them 0 - 2 like they were called on older SoCs.
- */
-#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
-#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
-#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19)
 #else
 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)