@@ -154,6 +154,13 @@ config NAND_MXS
if NAND_MXS
+config NAND_MXS_DT
+ bool "Support MXS NAND controller as a DT device"
+ depends on OF_CONTROL && MTD
+ help
+ Enable the driver for MXS NAND flash on platforms using
+ device tree.
+
config NAND_MXS_USE_MINIMUM_ECC
bool "Use minimum ECC strength supported by the controller"
default false
@@ -57,6 +57,7 @@ obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
+obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o
obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
@@ -1159,6 +1159,9 @@ int mxs_nand_init(struct mxs_nand_info *nand_info)
nand_set_controller_data(nand, nand_info);
nand->options |= NAND_NO_SUBPAGE_WRITE;
+ if (nand_info->dev)
+ nand->flash_node = dev_of_offset(nand_info->dev);
+
nand->cmd_ctrl = mxs_nand_cmd_ctrl;
nand->dev_ready = mxs_nand_device_ready;
@@ -1206,6 +1209,7 @@ err1:
return err;
}
+#ifndef CONFIG_NAND_MXS_DT
void board_nand_init(void)
{
struct mxs_nand_info *nand_info;
@@ -1232,3 +1236,4 @@ void board_nand_init(void)
mxs_nand_init(nand_info);
}
+#endif
new file mode 100644
@@ -0,0 +1,86 @@
+/*
+ * NXP GPMI NAND flash driver (DT initialization)
+ *
+ * Copyright (C) 2018 Toradex
+ * Authors:
+ * Stefan Agner <stefan.agner@toradex.com>
+ *
+ * Based on denali_dt.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/printk.h>
+
+#include "mxs_nand.h"
+
+struct mxs_nand_dt_data {
+ unsigned int max_ecc_strength_supported;
+};
+
+static const struct mxs_nand_dt_data mxs_nand_imx7d_data = {
+ .max_ecc_strength_supported = 62,
+};
+
+static const struct udevice_id mxs_nand_dt_ids[] = {
+ {
+ .compatible = "fsl,imx7d-gpmi-nand",
+ .data = (unsigned long)&mxs_nand_imx7d_data,
+ },
+ { /* sentinel */ }
+};
+
+static int mxs_nand_dt_probe(struct udevice *dev)
+{
+ struct mxs_nand_info *info = dev_get_priv(dev);
+ const struct mxs_nand_dt_data *data;
+ struct resource res;
+ int ret;
+
+ data = (void *)dev_get_driver_data(dev);
+ if (data)
+ info->max_ecc_strength_supported = data->max_ecc_strength_supported;
+
+ info->dev = dev;
+
+ ret = dev_read_resource_byname(dev, "gpmi-nand", &res);
+ if (ret)
+ return ret;
+
+ info->gpmi_regs = devm_ioremap(dev, res.start, resource_size(&res));
+
+
+ ret = dev_read_resource_byname(dev, "bch", &res);
+ if (ret)
+ return ret;
+
+ info->bch_regs = devm_ioremap(dev, res.start, resource_size(&res));
+
+ info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
+
+ return mxs_nand_init(info);
+}
+
+U_BOOT_DRIVER(mxs_nand_dt) = {
+ .name = "mxs-nand-dt",
+ .id = UCLASS_MTD,
+ .of_match = mxs_nand_dt_ids,
+ .probe = mxs_nand_dt_probe,
+ .priv_auto_alloc_size = sizeof(struct mxs_nand_info),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_GET_DRIVER(mxs_nand_dt),
+ &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize MXS NAND controller. (error %d)\n",
+ ret);
+}