diff mbox series

[U-Boot,v1,06/16] arm: socfpga: misc: Move eth reset to common misc driver

Message ID 1524131457-19234-7-git-send-email-ley.foon.tan@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series Add Intel Stratix 10 SoC support | expand

Commit Message

Ley Foon Tan April 19, 2018, 9:50 a.m. UTC 
Move eth reset to common misc driver so can used by other device families.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/include/mach/misc.h |    1 +
 arch/arm/mach-socfpga/misc.c              |   69 +++++++++++++++++++++++++++
 arch/arm/mach-socfpga/misc_gen5.c         |   74 +----------------------------
 3 files changed, 72 insertions(+), 72 deletions(-)

Comments

Marek Vasut April 19, 2018, 2:47 a.m. UTC | #1 
On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Move eth reset to common misc driver so can used by other device families.
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Shouldn't this use the reset framework instead ?
Ley Foon Tan April 19, 2018, 3:13 a.m. UTC | #2 
On Thu, Apr 19, 2018 at 10:47 AM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Move eth reset to common misc driver so can used by other device families.
>>
>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>
> Shouldn't this use the reset framework instead ?
>
What reset framework you refer to? drivers/reset?
Marek Vasut April 19, 2018, 8:20 a.m. UTC | #3 
On 04/19/2018 05:13 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 10:47 AM, Marek Vasut <marex@denx.de> wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>> Move eth reset to common misc driver so can used by other device families.
>>>
>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>
>> Shouldn't this use the reset framework instead ?
>>
> What reset framework you refer to? drivers/reset?

I think so, there were patches from Dinh earlier this month
 2ac718821a   | Dinh Nguyen  | reset: socfpga: add reset driver for
SoCFPGA platform
Ley Foon Tan April 23, 2018, 1:31 a.m. UTC | #4 
On Thu, Apr 19, 2018 at 4:20 PM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 05:13 AM, Ley Foon Tan wrote:
>> On Thu, Apr 19, 2018 at 10:47 AM, Marek Vasut <marex@denx.de> wrote:
>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>> Move eth reset to common misc driver so can used by other device families.
>>>>
>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>
>>> Shouldn't this use the reset framework instead ?
>>>
>> What reset framework you refer to? drivers/reset?
>
> I think so, there were patches from Dinh earlier this month
>  2ac718821a   | Dinh Nguyen  | reset: socfpga: add reset driver for
> SoCFPGA platform
>
Noted, will remove this change.

Regards
Ley Foon
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 0b65783..8466023 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -8,6 +8,7 @@ 
 #define _MISC_H_
 
 void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
+int socfpga_eth_reset(void);
 
 struct bsel {
 	const char	*mode;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 01f824c..d15cbc7 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -140,3 +140,72 @@  int arch_cpu_init(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_ETH_DESIGNWARE
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+	if (!phymode)
+		return -EINVAL;
+
+	if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+		return 0;
+	}
+
+	if (!strcmp(phymode, "rgmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+		return 0;
+	}
+
+	if (!strcmp(phymode, "rmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+int socfpga_eth_reset(void)
+{
+	const void *fdt = gd->fdt_blob;
+	struct fdtdec_phandle_args args;
+	const char *phy_mode;
+	u32 phy_modereg;
+	int nodes[3];	/* Max. 3 GMACs */
+	int ret, count;
+	int i, node;
+
+	count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+					   COMPAT_ALTERA_SOCFPGA_DWMAC,
+					   nodes, ARRAY_SIZE(nodes));
+	for (i = 0; i < count; i++) {
+		node = nodes[i];
+		if (node <= 0)
+			continue;
+
+		ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+						     "#reset-cells", 1, 0,
+						     &args);
+		if (ret || args.args_count != 1) {
+			debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+			continue;
+		}
+
+		phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+		ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+		if (ret) {
+			debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+			continue;
+		}
+
+		dwmac_deassert_reset(args.args[0], phy_modereg);
+	}
+
+	return 0;
+}
+#else
+int socfpga_eth_reset(void)
+{
+	return 0;
+};
+#endif
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 177b35f..f642524 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -63,84 +63,13 @@  void dwmac_deassert_reset(const unsigned int of_reset_id,
 	/* Release the EMAC controller from reset */
 	socfpga_per_reset(reset, 0);
 }
-
-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
-	if (!phymode)
-		return -EINVAL;
-
-	if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
-		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
-		return 0;
-	}
-
-	if (!strcmp(phymode, "rgmii")) {
-		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
-		return 0;
-	}
-
-	if (!strcmp(phymode, "rmii")) {
-		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
-		return 0;
-	}
-
-	return -EINVAL;
-}
-
-static int socfpga_eth_reset(void)
-{
-	const void *fdt = gd->fdt_blob;
-	struct fdtdec_phandle_args args;
-	const char *phy_mode;
-	u32 phy_modereg;
-	int nodes[2];	/* Max. two GMACs */
-	int ret, count;
-	int i, node;
-
-	/* Put both GMACs into RESET state. */
-	socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
-	socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-
-	count = fdtdec_find_aliases_for_id(fdt, "ethernet",
-					   COMPAT_ALTERA_SOCFPGA_DWMAC,
-					   nodes, ARRAY_SIZE(nodes));
-	for (i = 0; i < count; i++) {
-		node = nodes[i];
-		if (node <= 0)
-			continue;
-
-		ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
-						     "#reset-cells", 1, 0,
-						     &args);
-		if (ret || (args.args_count != 1)) {
-			debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
-			continue;
-		}
-
-		phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
-		ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
-		if (ret) {
-			debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
-			continue;
-		}
-
-		dwmac_deassert_reset(args.args[0], phy_modereg);
-	}
-
-	return 0;
-}
-#else
-static int socfpga_eth_reset(void)
-{
-	return 0;
-};
 #endif
 
 static const struct {
 	const u16	pn;
 	const char	*name;
 	const char	*var;
-} socfpga_fpga_model[] = {
+} const socfpga_fpga_model[] = {
 	/* Cyclone V E */
 	{ 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
 	{ 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
@@ -218,6 +147,7 @@  int arch_misc_init(void)
 	env_set("bootmode", bsel_str[bsel].mode);
 	if (fpga_id >= 0)
 		env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
+
 	return socfpga_eth_reset();
 }
 #endif