From patchwork Tue Apr 17 18:42:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 899546 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-476499-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=intel.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="xEF5XcZO"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40QYyn2Wj7z9rxx for ; Wed, 18 Apr 2018 04:42:39 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type; q=dns; s=default; b=XOjX/wFoa40rZ03n0aQ8PLr5lAU1K WqEiz5yFxfpHcd1JoZSBAvG8rk5u7vy4d8XoDNS/eECCOwhTBdmYNn3BqFAqmcx3 h4R9Kh40Eu1bnCgGurSK551ijiDkoL01JlCPDNxYZYnfUR1s1mfvFB8jimFy4YsA KHWK+V/7fq3de0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type; s=default; bh=3SjiSmT9Mj1IbrVfFQ+Qh5kOGAw=; b=xEF 5XcZOCkgZJZpQvc1p7osAfJiDqtyZ4Ol7/THTn+r69AbhHjuLI378ErHPRGNbijj a0DmFU9VzK2Up0Gwt3tRx1yliUlZ/Zb7q7c9qvMJp1IBLbPJfwQ3oY0feSfwjCzG RNP2PzZ/ydjb1PDgC/W60BTv/EmLROWE1VNRbD64= Received: (qmail 124246 invoked by alias); 17 Apr 2018 18:42:31 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 123897 invoked by uid 89); 17 Apr 2018 18:42:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, NO_DNS_FOR_FROM autolearn=ham version=3.3.2 spammy=gate, punpcklbw, Verify, dgfinal X-HELO: mga05.intel.com Received: from mga05.intel.com (HELO mga05.intel.com) (192.55.52.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 17 Apr 2018 18:42:28 +0000 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Apr 2018 11:42:25 -0700 X-ExtLoop1: 1 Received: from gnu-cfl-1.sc.intel.com ([172.25.70.237]) by orsmga007.jf.intel.com with ESMTP; 17 Apr 2018 11:42:25 -0700 Received: by gnu-cfl-1.sc.intel.com (Postfix, from userid 1000) id D6C01440ADC; Tue, 17 Apr 2018 11:42:24 -0700 (PDT) Date: Tue, 17 Apr 2018 11:42:24 -0700 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak , Igor Tsimbalist Subject: [PATCH] x86: Allow -fcf-protection with multi-byte NOPs Message-ID: <20180417184224.GA22831@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.9.2 (2017-12-15) -fcf-protection -mcet can't be used with IFUNC features, like symbol multiversioning or target clone, since IBT/SHSTK are applied to the whole program and they may be disabled in some functions. But -fcf-protection is implemented with multi-byte NOPs on all 64-bit processors as well as 32-bit processors starting with Pentium Pro. If -fcf-protection requires -mcet, IFUNC features can't be used on Linux when -fcf-protection is enabled by default. This patch changes -fcf-protection to to enable the NOP portion of CET ISAs unless IBT and/or SHSTK are disabled explicitly. The rest of CET ISAs, including intrinsics, still requires -mcet, -mibt or -mshstk. OK for trunk? H.J. --- gcc/ PR target/85417 * config/i386/cet.c (file_end_indicate_exec_stack_and_cet): Check flag_cf_protection instead of TARGET_IBT and TARGET_SHSTK. * config/i386/i386.c (pass_insert_endbranch::gate): Don't check TARGET_IBT. (ix86_option_override_internal): For -fcf-protection, set x_flag_cet to 1 if not set and also check x_flag_cet. (ix86_trampoline_init): Don't check TARGET_IBT. (x86_output_mi_thunk): Likewise. (ix86_notrack_prefixed_insn_p): Likewise. * config/i386/i386.md (rdssp): Also enable for flag_cet. (incssp): Likewise. (nop_endbr): Also enable for flag_cet. * config/i386/i386.opt (flag_cet): Initialized to -1. gcc/testsuite/ PR target/85417 * c-c++-common/attr-nocf-check-1.c: Compile with -fcf-protection=none. * c-c++-common/attr-nocf-check-3.c: Likewise. * gcc.dg/march-generic.c: Likewise. * gcc.target/i386/align-limit.c: Likewise. * c-c++-common/fcf-protection-1.c: Remove dg-error for x86 targets. * c-c++-common/fcf-protection-2.c: Likewise. * c-c++-common/fcf-protection-3.c: Likewise. * c-c++-common/fcf-protection-5.c: Likewise. * c-c++-common/fcf-protection-6.c: Remove dg-additional-options and dg-error for x86 targets. * c-c++-common/fcf-protection-7.c: Likewise. * gcc.target/i386/cet-notrack-icf-1.c: Compile with -fcf-protection=none -mno-cet. * gcc.target/i386/cet-notrack-icf-3.c: Likewise. * gcc.target/i386/cet-property-2.c: Compile with -fcf-protection=none. * gcc.target/i386/indirect-thunk-attr-7.c: Likewise. * gcc.target/i386/indirect-thunk-extern-7.c: Likewise. * gcc.target/i386/ret-thunk-26.c: Likewise. * gcc.target/i386/cet-label-3.c: New test. * gcc.target/i386/cet-property-3.c: Likewise. * gcc.target/i386/cet-sjlj-7.c: Likewise. * gcc.target/i386/pr85417-1.c: Likewise. * gcc.target/i386/pr85417-2.c: Likewise. --- gcc/config/i386/cet.c | 4 +- gcc/config/i386/i386.c | 23 +++++++---- gcc/config/i386/i386.md | 6 +-- gcc/config/i386/i386.opt | 2 +- gcc/testsuite/c-c++-common/attr-nocf-check-1.c | 1 + gcc/testsuite/c-c++-common/attr-nocf-check-3.c | 1 + gcc/testsuite/c-c++-common/fcf-protection-1.c | 1 - gcc/testsuite/c-c++-common/fcf-protection-2.c | 1 - gcc/testsuite/c-c++-common/fcf-protection-3.c | 1 - gcc/testsuite/c-c++-common/fcf-protection-5.c | 1 - gcc/testsuite/c-c++-common/fcf-protection-6.c | 3 +- gcc/testsuite/c-c++-common/fcf-protection-7.c | 3 +- gcc/testsuite/gcc.dg/march-generic.c | 2 +- gcc/testsuite/gcc.target/i386/align-limit.c | 2 +- gcc/testsuite/gcc.target/i386/cet-label-3.c | 16 ++++++++ gcc/testsuite/gcc.target/i386/cet-notrack-icf-1.c | 2 +- gcc/testsuite/gcc.target/i386/cet-notrack-icf-3.c | 2 +- gcc/testsuite/gcc.target/i386/cet-property-2.c | 2 +- gcc/testsuite/gcc.target/i386/cet-property-3.c | 11 +++++ gcc/testsuite/gcc.target/i386/cet-sjlj-7.c | 48 ++++++++++++++++++++++ .../gcc.target/i386/indirect-thunk-attr-7.c | 2 +- .../gcc.target/i386/indirect-thunk-extern-7.c | 2 +- gcc/testsuite/gcc.target/i386/pr85417-1.c | 4 ++ gcc/testsuite/gcc.target/i386/pr85417-2.c | 17 ++++++++ gcc/testsuite/gcc.target/i386/ret-thunk-26.c | 2 +- 25 files changed, 129 insertions(+), 30 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/cet-label-3.c create mode 100644 gcc/testsuite/gcc.target/i386/cet-property-3.c create mode 100644 gcc/testsuite/gcc.target/i386/cet-sjlj-7.c create mode 100644 gcc/testsuite/gcc.target/i386/pr85417-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr85417-2.c diff --git a/gcc/config/i386/cet.c b/gcc/config/i386/cet.c index 4a1e013fdde..eb3be171471 100644 --- a/gcc/config/i386/cet.c +++ b/gcc/config/i386/cet.c @@ -34,11 +34,11 @@ file_end_indicate_exec_stack_and_cet (void) unsigned int feature_1 = 0; - if (TARGET_IBT) + if (flag_cf_protection & CF_BRANCH) /* GNU_PROPERTY_X86_FEATURE_1_IBT. */ feature_1 |= 0x1; - if (TARGET_SHSTK) + if (flag_cf_protection & CF_RETURN) /* GNU_PROPERTY_X86_FEATURE_1_SHSTK. */ feature_1 |= 0x2; diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 9074526b8a1..5e96e19a0fb 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2701,7 +2701,7 @@ public: /* opt_pass methods: */ virtual bool gate (function *) { - return ((flag_cf_protection & CF_BRANCH) && TARGET_IBT); + return ((flag_cf_protection & CF_BRANCH)); } virtual unsigned int execute (function *) @@ -4936,10 +4936,15 @@ ix86_option_override_internal (bool main_args_p, = (cf_protection_level) (opts->x_flag_cf_protection & ~CF_SET); if (cf_protection != CF_NONE) { + /* Since -fcf-protection is implemented with multi-byte NOPs on + all 64-bit processors as well as 32-bit processors starting + with Pentium Pro, allow -fcf-protection to enable the NOP + portion of CET unless CET is disabled explicitly. */ switch (cf_protection) { case CF_BRANCH: - if (! TARGET_IBT_P (opts->x_ix86_isa_flags2)) + if (!TARGET_IBT_P (opts->x_ix86_isa_flags2) + && opts->x_flag_cet >= 0) { error ("%<-fcf-protection=branch%> requires Intel CET " "support. Use -mcet or -mibt option to enable CET"); @@ -4948,7 +4953,8 @@ ix86_option_override_internal (bool main_args_p, } break; case CF_RETURN: - if (! TARGET_SHSTK_P (opts->x_ix86_isa_flags)) + if (!TARGET_SHSTK_P (opts->x_ix86_isa_flags) + && opts->x_flag_cet >= 0) { error ("%<-fcf-protection=return%> requires Intel CET " "support. Use -mcet or -mshstk option to enable CET"); @@ -4957,8 +4963,9 @@ ix86_option_override_internal (bool main_args_p, } break; case CF_FULL: - if ( ! TARGET_IBT_P (opts->x_ix86_isa_flags2) - || ! TARGET_SHSTK_P (opts->x_ix86_isa_flags)) + if ((!TARGET_IBT_P (opts->x_ix86_isa_flags2) + || !TARGET_SHSTK_P (opts->x_ix86_isa_flags)) + && opts->x_flag_cet >= 0) { error ("%<-fcf-protection=full%> requires Intel CET " "support. Use -mcet or both of -mibt and " @@ -30399,7 +30406,7 @@ ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) rtx mem, fnaddr; int opcode; int offset = 0; - bool need_endbr = (flag_cf_protection & CF_BRANCH) && TARGET_IBT; + bool need_endbr = (flag_cf_protection & CF_BRANCH); fnaddr = XEXP (DECL_RTL (fndecl), 0); @@ -41757,7 +41764,7 @@ x86_output_mi_thunk (FILE *file, tree, HOST_WIDE_INT delta, emit_note (NOTE_INSN_PROLOGUE_END); /* CET is enabled, insert EB instruction. */ - if ((flag_cf_protection & CF_BRANCH) && TARGET_IBT) + if ((flag_cf_protection & CF_BRANCH)) emit_insn (gen_nop_endbr ()); /* If VCALL_OFFSET, we'll need THIS in a register. Might as well @@ -49757,7 +49764,7 @@ ix86_bnd_prefixed_insn_p (rtx insn) static bool ix86_notrack_prefixed_insn_p (rtx insn) { - if (!insn || !((flag_cf_protection & CF_BRANCH) && TARGET_IBT)) + if (!insn || !((flag_cf_protection & CF_BRANCH))) return false; if (CALL_P (insn)) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 352212094ec..b7bd71dc3ec 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -20278,7 +20278,7 @@ (define_insn "rdssp" [(set (match_operand:SWI48x 0 "register_operand" "=r") (unspec_volatile:SWI48x [(const_int 0)] UNSPECV_NOP_RDSSP))] - "TARGET_SHSTK" + "TARGET_SHSTK || flag_cet" "xor{l}\t%k0, %k0\n\trdssp\t%0" [(set_attr "length" "6") (set_attr "type" "other")]) @@ -20286,7 +20286,7 @@ (define_insn "incssp" [(unspec_volatile [(match_operand:SWI48x 0 "register_operand" "r")] UNSPECV_INCSSP)] - "TARGET_SHSTK" + "TARGET_SHSTK || flag_cet" "incssp\t%0" [(set_attr "length" "4") (set_attr "type" "other")]) @@ -20341,7 +20341,7 @@ (define_insn "nop_endbr" [(unspec_volatile [(const_int 0)] UNSPECV_NOP_ENDBR)] - "TARGET_IBT" + "TARGET_IBT || flag_cet" "* { return (TARGET_64BIT)? \"endbr64\" : \"endbr32\"; }" [(set_attr "length" "4") diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index c063ae8b1ae..dea8551bf7f 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1007,7 +1007,7 @@ Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save Generate code which uses only the general registers. mcet -Target Report Var(flag_cet) Init(0) +Target Report Var(flag_cet) Init(-1) Support Control-flow Enforcement Technology (CET) built-in functions and code generation. diff --git a/gcc/testsuite/c-c++-common/attr-nocf-check-1.c b/gcc/testsuite/c-c++-common/attr-nocf-check-1.c index 15f69731b91..c5ac7cb9f86 100644 --- a/gcc/testsuite/c-c++-common/attr-nocf-check-1.c +++ b/gcc/testsuite/c-c++-common/attr-nocf-check-1.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-additional-options "-fcf-protection=none" } */ int func (int) __attribute__ ((nocf_check)); /* { dg-warning "'nocf_check' attribute ignored" } */ int (*fptr) (int) __attribute__ ((nocf_check)); /* { dg-warning "'nocf_check' attribute ignored" } */ diff --git a/gcc/testsuite/c-c++-common/attr-nocf-check-3.c b/gcc/testsuite/c-c++-common/attr-nocf-check-3.c index ad1ca7eec9b..02b56cb155e 100644 --- a/gcc/testsuite/c-c++-common/attr-nocf-check-3.c +++ b/gcc/testsuite/c-c++-common/attr-nocf-check-3.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-additional-options "-fcf-protection=none" } */ int foo (void) __attribute__ ((nocf_check)); /* { dg-warning "'nocf_check' attribute ignored" } */ void (*foo1) (void) __attribute__((nocf_check)); /* { dg-warning "'nocf_check' attribute ignored" } */ diff --git a/gcc/testsuite/c-c++-common/fcf-protection-1.c b/gcc/testsuite/c-c++-common/fcf-protection-1.c index 8e71f47dde0..f59a8fbdfdc 100644 --- a/gcc/testsuite/c-c++-common/fcf-protection-1.c +++ b/gcc/testsuite/c-c++-common/fcf-protection-1.c @@ -1,4 +1,3 @@ /* { dg-do compile } */ /* { dg-options "-fcf-protection=full" } */ -/* { dg-error "'-fcf-protection=full' requires Intel CET.*-mcet.*-mibt and -mshstk option" "" { target { "i?86-*-* x86_64-*-*" } } 0 } */ /* { dg-error "'-fcf-protection=full' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ diff --git a/gcc/testsuite/c-c++-common/fcf-protection-2.c b/gcc/testsuite/c-c++-common/fcf-protection-2.c index d7d6db0e95d..61059725af6 100644 --- a/gcc/testsuite/c-c++-common/fcf-protection-2.c +++ b/gcc/testsuite/c-c++-common/fcf-protection-2.c @@ -1,4 +1,3 @@ /* { dg-do compile } */ /* { dg-options "-fcf-protection=branch" } */ -/* { dg-error "'-fcf-protection=branch' requires Intel CET.*-mcet or -mibt option" "" { target { "i?86-*-* x86_64-*-*" } } 0 } */ /* { dg-error "'-fcf-protection=branch' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ diff --git a/gcc/testsuite/c-c++-common/fcf-protection-3.c b/gcc/testsuite/c-c++-common/fcf-protection-3.c index 5b903c5fa51..257e944c4a6 100644 --- a/gcc/testsuite/c-c++-common/fcf-protection-3.c +++ b/gcc/testsuite/c-c++-common/fcf-protection-3.c @@ -1,4 +1,3 @@ /* { dg-do compile } */ /* { dg-options "-fcf-protection=return" } */ -/* { dg-error "'-fcf-protection=return' requires Intel CET.*-mcet or -mshstk option" "" { target { "i?86-*-* x86_64-*-*" } } 0 } */ /* { dg-error "'-fcf-protection=return' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ diff --git a/gcc/testsuite/c-c++-common/fcf-protection-5.c b/gcc/testsuite/c-c++-common/fcf-protection-5.c index d7a67801e2e..dc317f84b07 100644 --- a/gcc/testsuite/c-c++-common/fcf-protection-5.c +++ b/gcc/testsuite/c-c++-common/fcf-protection-5.c @@ -1,4 +1,3 @@ /* { dg-do compile } */ /* { dg-options "-fcf-protection" } */ -/* { dg-error "'-fcf-protection=full' requires Intel CET.*-mcet.*-mibt and -mshstk option" "" { target { "i?86-*-* x86_64-*-*" } } 0 } */ /* { dg-error "'-fcf-protection=full' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ diff --git a/gcc/testsuite/c-c++-common/fcf-protection-6.c b/gcc/testsuite/c-c++-common/fcf-protection-6.c index 532e76e6915..a1e919a2f63 100644 --- a/gcc/testsuite/c-c++-common/fcf-protection-6.c +++ b/gcc/testsuite/c-c++-common/fcf-protection-6.c @@ -1,5 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-fcf-protection=branch" } */ -/* { dg-additional-options "-mshstk" { target { i?86-*-* x86_64-*-* } } } */ -/* { dg-error "'-fcf-protection=branch' requires Intel CET.*-mcet or -mibt option" "" { target { "i?86-*-* x86_64-*-*" } } 0 } */ +/* { dg-additional-options "-mshstk -mno-ibt" { target { i?86-*-* x86_64-*-* } } } */ /* { dg-error "'-fcf-protection=branch' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ diff --git a/gcc/testsuite/c-c++-common/fcf-protection-7.c b/gcc/testsuite/c-c++-common/fcf-protection-7.c index 4c879692708..9e89becdaad 100644 --- a/gcc/testsuite/c-c++-common/fcf-protection-7.c +++ b/gcc/testsuite/c-c++-common/fcf-protection-7.c @@ -1,5 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-fcf-protection=return" } */ -/* { dg-additional-options "-mibt" { target { i?86-*-* x86_64-*-* } } } */ -/* { dg-error "'-fcf-protection=return' requires Intel CET.*-mcet or -mshstk option" "" { target { "i?86-*-* x86_64-*-*" } } 0 } */ +/* { dg-additional-options "-mibt -mno-shstk" { target { i?86-*-* x86_64-*-* } } } */ /* { dg-error "'-fcf-protection=return' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.dg/march-generic.c b/gcc/testsuite/gcc.dg/march-generic.c index fb5b83c7d74..f9c00e4a1c1 100644 --- a/gcc/testsuite/gcc.dg/march-generic.c +++ b/gcc/testsuite/gcc.dg/march-generic.c @@ -1,6 +1,6 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ /* { dg-skip-if "" { *-*-* } { "-march=*" } { "" } } */ -/* { dg-options "-march=generic" } */ +/* { dg-options "-march=generic -fcf-protection=none" } */ /* { dg-error "'generic' CPU can be used only for '-mtune=' switch" "" { target *-*-* } 0 } */ /* { dg-bogus "march" "" { target *-*-* } 0 } */ int i; diff --git a/gcc/testsuite/gcc.target/i386/align-limit.c b/gcc/testsuite/gcc.target/i386/align-limit.c index d3d8dc5656e..849d741189c 100644 --- a/gcc/testsuite/gcc.target/i386/align-limit.c +++ b/gcc/testsuite/gcc.target/i386/align-limit.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -falign-functions=64 -flimit-function-alignment -march=amdfam10" } */ +/* { dg-options "-O2 -falign-functions=64 -flimit-function-alignment -march=amdfam10 -fcf-protection=none" } */ /* { dg-final { scan-assembler ".p2align 6,,1" } } */ /* { dg-final { scan-assembler-not ".p2align 6,,63" } } */ diff --git a/gcc/testsuite/gcc.target/i386/cet-label-3.c b/gcc/testsuite/gcc.target/i386/cet-label-3.c new file mode 100644 index 00000000000..ae3ea632a27 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cet-label-3.c @@ -0,0 +1,16 @@ +/* Verify that CET works. */ +/* { dg-do compile } */ +/* { dg-options "-O -fcf-protection" } */ +/* { dg-final { scan-assembler-times "endbr32" 3 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "endbr64" 3 { target { ! ia32 } } } } */ + +int func (int arg) +{ + static void *array[] = { &&foo, &&bar }; + + goto *array[arg]; +foo: + return arg*111; +bar: + return arg*777; +} diff --git a/gcc/testsuite/gcc.target/i386/cet-notrack-icf-1.c b/gcc/testsuite/gcc.target/i386/cet-notrack-icf-1.c index 7987d53d305..00a3f3e5d5f 100644 --- a/gcc/testsuite/gcc.target/i386/cet-notrack-icf-1.c +++ b/gcc/testsuite/gcc.target/i386/cet-notrack-icf-1.c @@ -1,6 +1,6 @@ /* Verify nocf_check functions are not ICF optimized. */ /* { dg-do compile } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -fcf-protection=none -mno-cet" } */ /* { dg-final { scan-assembler-not "endbr" } } */ /* { dg-final { scan-assembler-not "fn3:" } } */ /* { dg-final { scan-assembler "set\[ \t]+fn2,fn1" } } */ diff --git a/gcc/testsuite/gcc.target/i386/cet-notrack-icf-3.c b/gcc/testsuite/gcc.target/i386/cet-notrack-icf-3.c index 07c4a6b61ef..c8b26f947d3 100644 --- a/gcc/testsuite/gcc.target/i386/cet-notrack-icf-3.c +++ b/gcc/testsuite/gcc.target/i386/cet-notrack-icf-3.c @@ -1,6 +1,6 @@ /* Verify nocf_check function calls are not ICF optimized. */ /* { dg-do compile } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -fcf-protection=none -mno-cet" } */ /* { dg-final { scan-assembler-not "endbr" } } */ /* { dg-final { scan-assembler-not "fn2:" } } */ /* { dg-final { scan-assembler "set\[ \t]+fn2,fn1" } } */ diff --git a/gcc/testsuite/gcc.target/i386/cet-property-2.c b/gcc/testsuite/gcc.target/i386/cet-property-2.c index 5a87dab92f1..bca6f6cdeb7 100644 --- a/gcc/testsuite/gcc.target/i386/cet-property-2.c +++ b/gcc/testsuite/gcc.target/i386/cet-property-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mcet" } */ +/* { dg-options "-mcet -fcf-protection=none" } */ /* { dg-final { scan-assembler-not ".note.gnu.property" } } */ extern void foo (void); diff --git a/gcc/testsuite/gcc.target/i386/cet-property-3.c b/gcc/testsuite/gcc.target/i386/cet-property-3.c new file mode 100644 index 00000000000..3e211c970aa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cet-property-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-fcf-protection" } */ +/* { dg-final { scan-assembler ".note.gnu.property" } } */ + +extern void foo (void); + +void +bar (void) +{ + foo (); +} diff --git a/gcc/testsuite/gcc.target/i386/cet-sjlj-7.c b/gcc/testsuite/gcc.target/i386/cet-sjlj-7.c new file mode 100644 index 00000000000..1b624327d0f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cet-sjlj-7.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fcf-protection" } */ +/* { dg-final { scan-assembler-times "endbr32" 2 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "endbr64" 2 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "call _?setjmp" 1 } } */ +/* { dg-final { scan-assembler-times "call longjmp" 1 } } */ + +#include +#include + +jmp_buf buf; +static int bar (int); + +__attribute__ ((noinline, noclone)) +static int +foo (int i) +{ + int j = i * 11; + + if (!setjmp (buf)) + { + j += 33; + printf ("After setjmp: j = %d\n", j); + bar (j); + } + + return j + i; +} + +__attribute__ ((noinline, noclone)) +static int +bar (int i) +{ + int j = i; + + j -= 111; + printf ("In longjmp: j = %d\n", j); + longjmp (buf, 1); + + return j; +} + +int +main () +{ + foo (10); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c index d53fc887dcc..5c120519ad9 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic" } */ +/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic -fcf-protection=none" } */ void func0 (void); void func1 (void); diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c index 2b9a33e93dc..74af6198bf4 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */ +/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic -fcf-protection=none" } */ void func0 (void); void func1 (void); diff --git a/gcc/testsuite/gcc.target/i386/pr85417-1.c b/gcc/testsuite/gcc.target/i386/pr85417-1.c new file mode 100644 index 00000000000..ee345961b73 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr85417-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-march=native -fcf-protection" } */ + +int foo; diff --git a/gcc/testsuite/gcc.target/i386/pr85417-2.c b/gcc/testsuite/gcc.target/i386/pr85417-2.c new file mode 100644 index 00000000000..17d52403744 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr85417-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-O3 -fcf-protection" } */ +/* { dg-final { scan-assembler "vpshufb" } } */ +/* { dg-final { scan-assembler "punpcklbw" } } */ + +__attribute__((target_clones("arch=core-avx2","arch=slm","default"))) +void +foo(char *in, char *out, int size) +{ + int i; + for(i = 0; i < size; i++) + { + out[2 * i] = in[i]; + out[2 * i + 1] = in[i]; + } +} diff --git a/gcc/testsuite/gcc.target/i386/ret-thunk-26.c b/gcc/testsuite/gcc.target/i386/ret-thunk-26.c index 9144e988735..dc722c2f5f9 100644 --- a/gcc/testsuite/gcc.target/i386/ret-thunk-26.c +++ b/gcc/testsuite/gcc.target/i386/ret-thunk-26.c @@ -1,6 +1,6 @@ /* PR target/r84530 */ /* { dg-do run } */ -/* { dg-options "-Os -mfunction-return=thunk" } */ +/* { dg-options "-Os -mfunction-return=thunk -fcf-protection=none" } */ struct S { int i; }; __attribute__((const, noinline, noclone))