@@ -80,6 +80,13 @@
#endif
#endif
+/* The TSEC driver uses the PHYLIB infrastructure */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_FMAN_ENET)
+#define CONFIG_PHYLIB
+
+#include <phylib_all_drivers.h>
+#endif /* PHYLIB-supporting ethernets */
+
/* All PPC boards must swap IDE bytes */
#define CONFIG_IDE_SWAP_IO
@@ -28,6 +28,16 @@ enum fsl_phy_enet_if {
FSL_ETH_IF_NONE,
};
+typedef struct tsec_mii_mng {
+ u32 miimcfg; /* MII management configuration reg */
+ u32 miimcom; /* MII management command reg */
+ u32 miimadd; /* MII management address reg */
+ u32 miimcon; /* MII management control reg */
+ u32 miimstat; /* MII management status reg */
+ u32 miimind; /* MII management indication reg */
+ u32 ifstat; /* Interface Status Register */
+} __attribute__ ((packed))tsec_mii_t;
+
int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc);
#endif /* __ASM_PPC_FSL_ENET_H */
@@ -21,6 +21,7 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
+#include <fsl_mdio.h>
#include "pci.h"
#include "../common/pq-mds-pib.h"
@@ -86,6 +87,7 @@ int board_mmc_init(bd_t *bd)
#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
int board_eth_init(bd_t *bd)
{
+ struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[2];
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
u32 rcwh = in_be32(&im->reset.rcwh);
@@ -131,6 +133,11 @@ int board_eth_init(bd_t *bd)
}
num++;
#endif
+
+ mdio_info.regs = (tsec_mii_t *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bd, &mdio_info);
+
return tsec_eth_init(bd, tsec_info, num);
}
@@ -36,6 +36,7 @@
#include <libfdt.h>
#include <spd_sdram.h>
#include <fdt_support.h>
+#include <fsl_mdio.h>
#include <tsec.h>
#include <netdev.h>
#include <sata.h>
@@ -234,6 +235,7 @@ int board_early_init_r(void)
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
+ struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[2];
int num = 0;
@@ -268,6 +270,10 @@ int board_eth_init(bd_t *bis)
}
#endif
+ mdio_info.regs = (tsec_mii_t *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
tsec_eth_init(bis, tsec_info, num);
#endif
return pci_eth_init(bis);
@@ -33,6 +33,7 @@
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <fsl_mdio.h>
#include <tsec.h>
#include <netdev.h>
@@ -248,9 +249,35 @@ get_board_sys_clk(ulong dummy)
return val;
}
+
+#define MIIM_CIS8204_SLED_CON 0x1b
+#define MIIM_CIS8204_SLEDCON_INIT 0x1115
+/*
+ * Hack to write all 4 PHYs with the LED values
+ */
+int board_phy_config(struct phy_device *phydev)
+{
+ static int do_once;
+ uint phyid;
+ struct mii_dev *bus = phydev->bus;
+
+ if (do_once)
+ return 0;
+
+ for (phyid = 0; phyid < 4; phyid++)
+ bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
+ MIIM_CIS8204_SLEDCON_INIT);
+
+ do_once = 1;
+
+ return 0;
+}
+
+
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
+ struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[2];
int num = 0;
@@ -282,6 +309,9 @@ int board_eth_init(bd_t *bis)
fsl_sgmii_riser_init(tsec_info, num);
}
+ mdio_info.regs = (tsec_mii_t *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#endif
@@ -35,6 +35,7 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>
+#include <fsl_mdio.h>
#include <netdev.h>
#include "../common/sgmii_riser.h"
@@ -187,6 +188,7 @@ int board_early_init_r(void)
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
+ struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
@@ -233,6 +235,10 @@ int board_eth_init(bd_t *bis)
fsl_sgmii_riser_init(tsec_info, num);
#endif
+ mdio_info.regs = (tsec_mii_t *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
tsec_eth_init(bis, tsec_info, num);
return pci_eth_init(bis);
@@ -22,6 +22,7 @@
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <fsl_mdio.h>
#include <tsec.h>
#include <asm/fsl_law.h>
#include <netdev.h>
@@ -245,6 +246,7 @@ int board_early_init_r(void)
*/
int board_eth_init(bd_t *bis)
{
+ struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[2];
unsigned int num = 0;
@@ -257,6 +259,10 @@ int board_eth_init(bd_t *bis)
num++;
#endif
+ mdio_info.regs = (tsec_mii_t *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
}
@@ -31,6 +31,7 @@
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <fsl_mdio.h>
#include <tsec.h>
#include <vsc7385.h>
#include <netdev.h>
@@ -179,6 +180,7 @@ int board_early_init_r(void)
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
+ struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
char *tmp;
@@ -216,6 +218,10 @@ int board_eth_init(bd_t *bis)
puts("No address specified for VSC7385 microcode.\n");
#endif
+ mdio_info.regs = (tsec_mii_t *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
tsec_eth_init(bis, tsec_info, num);
return pci_eth_init(bis);
@@ -34,6 +34,7 @@
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <fsl_mdio.h>
#include <tsec.h>
#include <asm/fsl_law.h>
#include <netdev.h>
@@ -201,6 +202,7 @@ int board_early_init_r(void)
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
+ struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
@@ -235,6 +237,11 @@ int board_eth_init(bd_t *bis)
fsl_sgmii_riser_init(tsec_info, num);
#endif
+ mdio_info.regs = (tsec_mii_t *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
tsec_eth_init(bis, tsec_info, num);
return pci_eth_init(bis);
@@ -79,7 +79,7 @@ COBJS-$(CONFIG_TIGON3) += tigon3.o
COBJS-$(CONFIG_TIGON3) += bcm570x_autoneg.o
COBJS-$(CONFIG_TIGON3) += 5701rls.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
-COBJS-$(CONFIG_TSEC_ENET) += tsec.o
+COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
COBJS-$(CONFIG_ULI526X) += uli526x.o
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
new file mode 100644
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Jun-jie Zhang <b18070@freescale.com>
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fsl_mdio.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/fsl_enet.h>
+
+void tsec_local_mdio_write(tsec_mii_t *phyregs, int port_addr,
+ int dev_addr, int regnum, int value)
+{
+ int timeout = 1000000;
+
+ out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
+ out_be32(&phyregs->miimcon, value);
+ asm("sync");
+
+ while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
+ ;
+}
+
+int tsec_local_mdio_read(tsec_mii_t *phyregs, int port_addr,
+ int dev_addr, int regnum)
+{
+ int value;
+ int timeout = 1000000;
+
+ /* Put the address of the phy, and the register
+ * number into MIIMADD */
+ out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
+
+ /* Clear the command register, and wait */
+ out_be32(&phyregs->miimcom, 0);
+ asm("sync");
+
+ /* Initiate a read command, and wait */
+ out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
+ asm("sync");
+
+ /* Wait for the the indication that the read is done */
+ while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
+ && timeout--)
+ ;
+
+ /* Grab the value read from the PHY */
+ value = in_be32(&phyregs->miimstat);
+
+ return value;
+}
+
+static int fsl_pq_mdio_reset(struct mii_dev *bus)
+{
+ tsec_mii_t *regs = bus->priv;
+
+ /* Reset MII (due to new addresses) */
+ out_be32(®s->miimcfg, MIIMCFG_RESET_MGMT);
+
+ out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE);
+
+ while (in_be32(®s->miimind) & MIIMIND_BUSY)
+ ;
+
+ return 0;
+}
+
+int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
+{
+ tsec_mii_t *phyregs = bus->priv;
+
+ return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
+}
+
+int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
+ u16 value)
+{
+ tsec_mii_t *phyregs = bus->priv;
+
+ tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
+
+ return 0;
+}
+
+int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate FSL MDIO bus\n");
+ return -1;
+ }
+
+ bus->read = tsec_phy_read;
+ bus->write = tsec_phy_write;
+ bus->reset = fsl_pq_mdio_reset;
+ sprintf(bus->name, info->name);
+
+ bus->priv = info->regs;
+
+ return mdio_register(bus);
+}
@@ -17,10 +17,9 @@
#include <net.h>
#include <command.h>
#include <tsec.h>
+#include <fsl_mdio.h>
#include <asm/errno.h>
-#include "miiphy.h"
-
DECLARE_GLOBAL_DATA_PTR;
#define TX_BUF_CNT 2
@@ -56,10 +55,10 @@ static struct tsec_info_struct tsec_info[] = {
#ifdef CONFIG_MPC85XX_FEC
{
.regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
- .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
.devname = CONFIG_MPC85XX_FEC_NAME,
.phyaddr = FEC_PHY_ADDR,
- .flags = FEC_FLAGS
+ .flags = FEC_FLAGS,
+ .mii_devname = DEFAULT_MII_NAME
}, /* FEC */
#endif
#ifdef CONFIG_TSEC3
@@ -70,61 +69,6 @@ static struct tsec_info_struct tsec_info[] = {
#endif
};
-/* Writes the given phy's reg with value, using the specified MDIO regs */
-static void tsec_local_mdio_write(tsec_mdio_t *phyregs, uint addr,
- uint reg, uint value)
-{
- int timeout = 1000000;
-
- out_be32(&phyregs->miimadd, (addr << 8) | reg);
- out_be32(&phyregs->miimcon, value);
- asm("sync");
-
- timeout = 1000000;
- while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
- ;
-}
-
-/* Provide the default behavior of writing the PHY of this ethernet device */
-#define write_phy_reg(priv, regnum, value) \
- tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
-
-/* Reads register regnum on the device's PHY through the
- * specified registers. It lowers and raises the read
- * command, and waits for the data to become valid (miimind
- * notvalid bit cleared), and the bus to cease activity (miimind
- * busy bit cleared), and then returns the value
- */
-static uint tsec_local_mdio_read(tsec_mdio_t *phyregs, uint phyid, uint regnum)
-{
- uint value;
-
- /* Put the address of the phy, and the register
- * number into MIIMADD */
- out_be32(&phyregs->miimadd, (phyid << 8) | regnum);
-
- /* Clear the command register, and wait */
- out_be32(&phyregs->miimcom, 0);
- asm("sync");
-
- /* Initiate a read command, and wait */
- out_be32(&phyregs->miimcom, MIIM_READ_COMMAND);
- asm("sync");
-
- /* Wait for the the indication that the read is done */
- while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY)))
- ;
-
- /* Grab the value read from the PHY */
- value = in_be32(&phyregs->miimstat);
-
- return value;
-}
-
-/* #define to provide old read_phy_reg functionality without duplicating code */
-#define read_phy_reg(priv,regnum) \
- tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
-
#define TBIANA_SETTINGS ( \
TBIANA_ASYMMETRIC_PAUSE \
| TBIANA_SYMMETRIC_PAUSE \
@@ -146,1408 +90,14 @@ static void tsec_configure_serdes(struct tsec_private *priv)
{
/* Access TBI PHY registers at given TSEC register offset as opposed
* to the register offset used for external PHY accesses */
- tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
- TBIANA_SETTINGS);
- tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
- TBICON_CLK_SELECT);
- tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
- CONFIG_TSEC_TBICR_SETTINGS);
-}
-
-/*
- * Returns which value to write to the control register.
- * For 10/100, the value is slightly different
- */
-static uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
-{
- if (priv->flags & TSEC_GIGABIT)
- return MIIM_CONTROL_INIT;
- else
- return MIIM_CR_INIT;
-}
-
-/*
- * Wait for auto-negotiation to complete, then determine link
- */
-static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
-{
- /*
- * Wait if the link is up, and autonegotiation is in progress
- * (ie - we're capable and it's not done)
- */
- mii_reg = read_phy_reg(priv, MIIM_STATUS);
- if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) {
- int i = 0;
-
- puts("Waiting for PHY auto negotiation to complete");
- while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
- /*
- * Timeout reached ?
- */
- if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts(" TIMEOUT !\n");
- priv->link = 0;
- return 0;
- }
-
- if (ctrlc()) {
- puts("user interrupt!\n");
- priv->link = 0;
- return -EINTR;
- }
-
- if ((i++ % 1000) == 0) {
- putc('.');
- }
- udelay(1000); /* 1 ms */
- mii_reg = read_phy_reg(priv, MIIM_STATUS);
- }
- puts(" done\n");
-
- /* Link status bit is latched low, read it again */
- mii_reg = read_phy_reg(priv, MIIM_STATUS);
-
- udelay(500000); /* another 500 ms (results in faster booting) */
- }
-
- priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0;
-
- return 0;
-}
-
-/* Generic function which updates the speed and duplex. If
- * autonegotiation is enabled, it uses the AND of the link
- * partner's advertised capabilities and our advertised
- * capabilities. If autonegotiation is disabled, we use the
- * appropriate bits in the control register.
- *
- * Stolen from Linux's mii.c and phy_device.c
- */
-static uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
-{
- /* We're using autonegotiation */
- if (mii_reg & BMSR_ANEGCAPABLE) {
- uint lpa = 0;
- uint gblpa = 0;
-
- /* Check for gigabit capability */
- if (mii_reg & BMSR_ERCAP) {
- /* We want a list of states supported by
- * both PHYs in the link
- */
- gblpa = read_phy_reg(priv, MII_STAT1000);
- gblpa &= read_phy_reg(priv, MII_CTRL1000) << 2;
- }
-
- /* Set the baseline so we only have to set them
- * if they're different
- */
- priv->speed = 10;
- priv->duplexity = 0;
-
- /* Check the gigabit fields */
- if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
- priv->speed = 1000;
-
- if (gblpa & PHY_1000BTSR_1000FD)
- priv->duplexity = 1;
-
- /* We're done! */
- return 0;
- }
-
- lpa = read_phy_reg(priv, MII_ADVERTISE);
- lpa &= read_phy_reg(priv, MII_LPA);
-
- if (lpa & (LPA_100FULL | LPA_100HALF)) {
- priv->speed = 100;
-
- if (lpa & LPA_100FULL)
- priv->duplexity = 1;
-
- } else if (lpa & LPA_10FULL)
- priv->duplexity = 1;
- } else {
- uint bmcr = read_phy_reg(priv, MII_BMCR);
-
- priv->speed = 10;
- priv->duplexity = 0;
-
- if (bmcr & BMCR_FULLDPLX)
- priv->duplexity = 1;
-
- if (bmcr & BMCR_SPEED1000)
- priv->speed = 1000;
- else if (bmcr & BMCR_SPEED100)
- priv->speed = 100;
- }
-
- return 0;
-}
-
-/*
- * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
- * circumstances. eg a gigabit TSEC connected to a gigabit switch with
- * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
- * link. "Ethernet@Wirespeed" reduces advertised speed until link
- * can be achieved.
- */
-static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv)
-{
- return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010;
-}
-
-/*
- * Parse the BCM54xx status register for speed and duplex information.
- * The linux sungem_phy has this information, but in a table format.
- */
-static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
-{
- /* If there is no link, speed and duplex don't matter */
- if (!priv->link)
- return 0;
-
- switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
- MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
- case 1:
- priv->duplexity = 0;
- priv->speed = 10;
- break;
- case 2:
- priv->duplexity = 1;
- priv->speed = 10;
- break;
- case 3:
- priv->duplexity = 0;
- priv->speed = 100;
- break;
- case 5:
- priv->duplexity = 1;
- priv->speed = 100;
- break;
- case 6:
- priv->duplexity = 0;
- priv->speed = 1000;
- break;
- case 7:
- priv->duplexity = 1;
- priv->speed = 1000;
- break;
- default:
- printf("Auto-neg error, defaulting to 10BT/HD\n");
- priv->duplexity = 0;
- priv->speed = 10;
- break;
- }
-
- return 0;
-}
-
-/*
- * Find out if PHY is in copper or serdes mode by looking at Expansion Reg
- * 0x42 - "Operating Mode Status Register"
- */
-static int BCM8482_is_serdes(struct tsec_private *priv)
-{
- u16 val;
- int serdes = 0;
-
- write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_ER | 0x42);
- val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA);
-
- switch (val & 0x1f) {
- case 0x0d: /* RGMII-to-100Base-FX */
- case 0x0e: /* RGMII-to-SGMII */
- case 0x0f: /* RGMII-to-SerDes */
- case 0x12: /* SGMII-to-SerDes */
- case 0x13: /* SGMII-to-100Base-FX */
- case 0x16: /* SerDes-to-Serdes */
- serdes = 1;
- break;
- case 0x6: /* RGMII-to-Copper */
- case 0x14: /* SGMII-to-Copper */
- case 0x17: /* SerDes-to-Copper */
- break;
- default:
- printf("ERROR, invalid PHY mode (0x%x\n)", val);
- break;
- }
-
- return serdes;
-}
-
-/*
- * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating
- * Mode Status Register"
- */
-uint mii_parse_BCM5482_serdes_sr(struct tsec_private *priv)
-{
- u16 val;
- int i = 0;
-
- /* Wait 1s for link - Clause 37 autonegotiation happens very fast */
- while (1) {
- write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL,
- MIIM_BCM54XX_EXP_SEL_ER | 0x42);
- val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA);
-
- if (val & 0x8000)
- break;
-
- if (i++ > 1000) {
- priv->link = 0;
- return 1;
- }
-
- udelay(1000); /* 1 ms */
- }
-
- priv->link = 1;
- switch ((val >> 13) & 0x3) {
- case (0x00):
- priv->speed = 10;
- break;
- case (0x01):
- priv->speed = 100;
- break;
- case (0x02):
- priv->speed = 1000;
- break;
- }
-
- priv->duplexity = (val & 0x1000) == 0x1000;
-
- return 0;
-}
-
-/*
- * Figure out if BCM5482 is in serdes or copper mode and determine link
- * configuration accordingly
- */
-static uint mii_parse_BCM5482_sr(uint mii_reg, struct tsec_private *priv)
-{
- if (BCM8482_is_serdes(priv)) {
- mii_parse_BCM5482_serdes_sr(priv);
- priv->flags |= TSEC_FIBER;
- } else {
- /* Wait for auto-negotiation to complete or fail */
- mii_parse_sr(mii_reg, priv);
-
- /* Parse BCM54xx copper aux status register */
- mii_reg = read_phy_reg(priv, MIIM_BCM54xx_AUXSTATUS);
- mii_parse_BCM54xx_sr(mii_reg, priv);
- }
-
- return 0;
-}
-
-/* Parse the 88E1011's status register for speed and duplex
- * information
- */
-static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
-{
- uint speed;
-
- mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
-
- if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
- !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
- int i = 0;
-
- puts("Waiting for PHY realtime link");
- while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
- /* Timeout reached ? */
- if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts(" TIMEOUT !\n");
- priv->link = 0;
- break;
- }
-
- if ((i++ % 1000) == 0) {
- putc('.');
- }
- udelay(1000); /* 1 ms */
- mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
- }
- puts(" done\n");
- udelay(500000); /* another 500 ms (results in faster booting) */
- } else {
- if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
- priv->link = 1;
- else
- priv->link = 0;
- }
-
- if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
- priv->duplexity = 1;
- else
- priv->duplexity = 0;
-
- speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
-
- switch (speed) {
- case MIIM_88E1011_PHYSTAT_GBIT:
- priv->speed = 1000;
- break;
- case MIIM_88E1011_PHYSTAT_100:
- priv->speed = 100;
- break;
- default:
- priv->speed = 10;
- }
-
- return 0;
-}
-
-/* Parse the RTL8211B's status register for speed and duplex
- * information
- */
-static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
-{
- uint speed;
-
- mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
- if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
- int i = 0;
-
- /* in case of timeout ->link is cleared */
- priv->link = 1;
- puts("Waiting for PHY realtime link");
- while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
- /* Timeout reached ? */
- if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts(" TIMEOUT !\n");
- priv->link = 0;
- break;
- }
-
- if ((i++ % 1000) == 0) {
- putc('.');
- }
- udelay(1000); /* 1 ms */
- mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
- }
- puts(" done\n");
- udelay(500000); /* another 500 ms (results in faster booting) */
- } else {
- if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
- priv->link = 1;
- else
- priv->link = 0;
- }
-
- if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
- priv->duplexity = 1;
- else
- priv->duplexity = 0;
-
- speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
-
- switch (speed) {
- case MIIM_RTL8211B_PHYSTAT_GBIT:
- priv->speed = 1000;
- break;
- case MIIM_RTL8211B_PHYSTAT_100:
- priv->speed = 100;
- break;
- default:
- priv->speed = 10;
- }
-
- return 0;
-}
-
-/* Parse the cis8201's status register for speed and duplex
- * information
- */
-static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
-{
- uint speed;
-
- if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
- priv->duplexity = 1;
- else
- priv->duplexity = 0;
-
- speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
- switch (speed) {
- case MIIM_CIS8201_AUXCONSTAT_GBIT:
- priv->speed = 1000;
- break;
- case MIIM_CIS8201_AUXCONSTAT_100:
- priv->speed = 100;
- break;
- default:
- priv->speed = 10;
- break;
- }
-
- return 0;
-}
-
-/* Parse the vsc8244's status register for speed and duplex
- * information
- */
-static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
-{
- uint speed;
-
- if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
- priv->duplexity = 1;
- else
- priv->duplexity = 0;
-
- speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
- switch (speed) {
- case MIIM_VSC8244_AUXCONSTAT_GBIT:
- priv->speed = 1000;
- break;
- case MIIM_VSC8244_AUXCONSTAT_100:
- priv->speed = 100;
- break;
- default:
- priv->speed = 10;
- break;
- }
-
- return 0;
-}
-
-/* Parse the DM9161's status register for speed and duplex
- * information
- */
-static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
-{
- if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
- priv->speed = 100;
- else
- priv->speed = 10;
-
- if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
- priv->duplexity = 1;
- else
- priv->duplexity = 0;
-
- return 0;
-}
-
-/*
- * Hack to write all 4 PHYs with the LED values
- */
-static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
-{
- uint phyid;
- tsec_mdio_t *regbase = priv->phyregs;
- int timeout = 1000000;
-
- for (phyid = 0; phyid < 4; phyid++) {
- out_be32(®base->miimadd, (phyid << 8) | mii_reg);
- out_be32(®base->miimcon, MIIM_CIS8204_SLEDCON_INIT);
- asm("sync");
-
- timeout = 1000000;
- while ((in_be32(®base->miimind) & MIIMIND_BUSY) && timeout--)
- ;
- }
-
- return MIIM_CIS8204_SLEDCON_INIT;
-}
-
-static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
-{
- if (priv->flags & TSEC_REDUCED)
- return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
- else
- return MIIM_CIS8204_EPHYCON_INIT;
-}
-
-static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
-{
- uint mii_data = read_phy_reg(priv, mii_reg);
-
- if (priv->flags & TSEC_REDUCED)
- mii_data = (mii_data & 0xfff0) | 0x000b;
- return mii_data;
-}
-
-static struct phy_info phy_info_M88E1149S = {
- 0x1410ca,
- "Marvell 88E1149S",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {0x1d, 0x1f, NULL},
- {0x1e, 0x200c, NULL},
- {0x1d, 0x5, NULL},
- {0x1e, 0x0, NULL},
- {0x1e, 0x100, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-/* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
-static struct phy_info phy_info_BCM5461S = {
- 0x02060c1, /* 5461 ID */
- "Broadcom BCM5461S",
- 0, /* not clear to me what minor revisions we can shift away */
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_BCM5464S = {
- 0x02060b1, /* 5464 ID */
- "Broadcom BCM5464S",
- 0, /* not clear to me what minor revisions we can shift away */
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_BCM5482S = {
- 0x0143bcb,
- "Broadcom BCM5482S",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- /* Setup read from auxilary control shadow register 7 */
- {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
- /* Read Misc Control register and or in Ethernet@Wirespeed */
- {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- /* Initial config/enable of secondary SerDes interface */
- {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf), NULL},
- /* Write intial value to secondary SerDes Contol */
- {MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_SSD | 0, NULL},
- {MIIM_BCM54XX_EXP_DATA, MIIM_CONTROL_RESTART, NULL},
- /* Enable copper/fiber auto-detect */
- {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Determine copper/fiber, auto-negotiate, and read the result */
- {MIIM_STATUS, miim_read, &mii_parse_BCM5482_sr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_M88E1011S = {
- 0x01410c6,
- "Marvell 88E1011S",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {0x1d, 0x1f, NULL},
- {0x1e, 0x200c, NULL},
- {0x1d, 0x5, NULL},
- {0x1e, 0x0, NULL},
- {0x1e, 0x100, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_M88E1111S = {
- 0x01410cc,
- "Marvell 88E1111S",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {0x1b, 0x848f, &mii_m88e1111s_setmode},
- {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_M88E1118 = {
- 0x01410e1,
- "Marvell 88E1118",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {0x16, 0x0002, NULL}, /* Change Page Number */
- {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
- {0x16, 0x0003, NULL}, /* Change Page Number */
- {0x10, 0x021e, NULL}, /* Adjust LED control */
- {0x16, 0x0000, NULL}, /* Change Page Number */
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- {0x16, 0x0000, NULL}, /* Change Page Number */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_88E1011_PHY_STATUS, miim_read,
- &mii_parse_88E1011_psr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-/*
- * Since to access LED register we need do switch the page, we
- * do LED configuring in the miim_read-like function as follows
- */
-static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
-{
- uint pg;
-
- /* Switch the page to access the led register */
- pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
- write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
-
- /* Configure leds */
- write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
- MIIM_88E1121_PHY_LED_DEF);
-
- /* Restore the page pointer */
- write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
- return 0;
-}
-
-static struct phy_info phy_info_M88E1121R = {
- 0x01410cb,
- "Marvell 88E1121R",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- /* Configure leds */
- {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- /* Disable IRQs and de-assert interrupt */
- {MIIM_88E1121_PHY_IRQ_EN, 0, NULL},
- {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- {MIIM_STATUS, miim_read, &mii_parse_link},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
-{
- uint mii_data = read_phy_reg(priv, mii_reg);
-
- /* Setting MIIM_88E1145_PHY_EXT_CR */
- if (priv->flags & TSEC_REDUCED)
- return mii_data |
- MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
- else
- return mii_data;
-}
-
-static struct phy_info phy_info_M88E1145 = {
- 0x01410cd,
- "Marvell 88E1145",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Reset the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
-
- /* Errata E0, E1 */
- {29, 0x001b, NULL},
- {30, 0x418f, NULL},
- {29, 0x0016, NULL},
- {30, 0xa2da, NULL},
-
- /* Configure the PHY */
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
- {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
- /* Read the Status */
- {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_cis8204 = {
- 0x3f11,
- "Cicada Cis8204",
- 6,
- (struct phy_cmd[]) { /* config */
- /* Override PHY config settings */
- {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
- &mii_cis8204_fixled},
- {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
- &mii_cis8204_setmode},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-/* Cicada 8201 */
-static struct phy_info phy_info_cis8201 = {
- 0xfc41,
- "CIS8201",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Override PHY config settings */
- {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
- /* Set up the interface mode */
- {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_VSC8211 = {
- 0xfc4b,
- "Vitesse VSC8211",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Override PHY config settings */
- {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
- /* Set up the interface mode */
- {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_VSC8244 = {
- 0x3f1b,
- "Vitesse VSC8244",
- 6,
- (struct phy_cmd[]) { /* config */
- /* Override PHY config settings */
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_VSC8641 = {
- 0x7043,
- "Vitesse VSC8641",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_VSC8221 = {
- 0xfc55,
- "Vitesse VSC8221",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_VSC8601 = {
- 0x00007042,
- "Vitesse VSC8601",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Override PHY config settings */
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
-#ifdef CONFIG_SYS_VSC8601_SKEWFIX
- {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
-#if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
- {MIIM_EXT_PAGE_ACCESS,1,NULL},
-#define VSC8101_SKEW \
- (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12)
- {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
- {MIIM_EXT_PAGE_ACCESS,0,NULL},
-#endif
-#endif
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_dm9161 = {
- 0x0181b88,
- "Davicom DM9161E",
- 4,
- (struct phy_cmd[]) { /* config */
- {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
- /* Do not bypass the scrambler/descrambler */
- {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
- /* Clear 10BTCSR to default */
- {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CR_INIT, NULL},
- /* Restart Auto Negotiation */
- {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-/* micrel KSZ804 */
-static struct phy_info phy_info_ksz804 = {
- 0x0022151,
- "Micrel KSZ804 PHY",
- 4,
- (struct phy_cmd[]) { /* config */
- {MII_BMCR, BMCR_RESET, NULL},
- {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- {MII_BMSR, miim_read, NULL},
- {MII_BMSR, miim_read, &mii_parse_sr},
- {MII_BMSR, miim_read, &mii_parse_link},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- }
-};
-
-/* a generic flavor. */
-static struct phy_info phy_info_generic = {
- 0,
- "Unknown/Generic PHY",
- 32,
- (struct phy_cmd[]) { /* config */
- {MII_BMCR, BMCR_RESET, NULL},
- {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- {MII_BMSR, miim_read, NULL},
- {MII_BMSR, miim_read, &mii_parse_sr},
- {MII_BMSR, miim_read, &mii_parse_link},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- }
-};
-
-static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
-{
- unsigned int speed;
- if (priv->link) {
- speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
-
- switch (speed) {
- case MIIM_LXT971_SR2_10HDX:
- priv->speed = 10;
- priv->duplexity = 0;
- break;
- case MIIM_LXT971_SR2_10FDX:
- priv->speed = 10;
- priv->duplexity = 1;
- break;
- case MIIM_LXT971_SR2_100HDX:
- priv->speed = 100;
- priv->duplexity = 0;
- break;
- default:
- priv->speed = 100;
- priv->duplexity = 1;
- }
- } else {
- priv->speed = 0;
- priv->duplexity = 0;
- }
-
- return 0;
-}
-
-static struct phy_info phy_info_lxt971 = {
- 0x0001378e,
- "LXT971",
- 4,
- (struct phy_cmd[]) { /* config */
- {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup - enable interrupts */
- /* { 0x12, 0x00f2, NULL }, */
- {MIIM_STATUS, miim_read, NULL},
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown - disable interrupts */
- {miim_end,}
- },
-};
-
-/* Parse the DP83865's link and auto-neg status register for speed and duplex
- * information
- */
-static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
-{
- switch (mii_reg & MIIM_DP83865_SPD_MASK) {
-
- case MIIM_DP83865_SPD_1000:
- priv->speed = 1000;
- break;
-
- case MIIM_DP83865_SPD_100:
- priv->speed = 100;
- break;
-
- default:
- priv->speed = 10;
- break;
-
- }
-
- if (mii_reg & MIIM_DP83865_DPX_FULL)
- priv->duplexity = 1;
- else
- priv->duplexity = 0;
-
- return 0;
+ tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
+ 0, TBI_ANA, TBIANA_SETTINGS);
+ tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
+ 0, TBI_TBICON, TBICON_CLK_SELECT);
+ tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
+ 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
}
-static struct phy_info phy_info_dp83865 = {
- 0x20005c7,
- "NatSemi DP83865",
- 4,
- (struct phy_cmd[]) { /* config */
- {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the link and auto-neg status */
- {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-static struct phy_info phy_info_rtl8211b = {
- 0x001cc91,
- "RealTek RTL8211B",
- 4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
-};
-
-struct phy_info phy_info_AR8021 = {
- 0x4dd04,
- "AR8021",
- 4,
- (struct phy_cmd[]) { /* config */
- {MII_BMCR, BMCR_RESET, NULL},
- {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
- {0x1d, 0x05, NULL},
- {0x1e, 0x3D47, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- {MII_BMSR, miim_read, NULL},
- {MII_BMSR, miim_read, &mii_parse_sr},
- {MII_BMSR, miim_read, &mii_parse_link},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- }
-};
-
-static struct phy_info *phy_info[] = {
- &phy_info_cis8204,
- &phy_info_cis8201,
- &phy_info_BCM5461S,
- &phy_info_BCM5464S,
- &phy_info_BCM5482S,
- &phy_info_M88E1011S,
- &phy_info_M88E1111S,
- &phy_info_M88E1118,
- &phy_info_M88E1121R,
- &phy_info_M88E1145,
- &phy_info_M88E1149S,
- &phy_info_dm9161,
- &phy_info_ksz804,
- &phy_info_lxt971,
- &phy_info_VSC8211,
- &phy_info_VSC8244,
- &phy_info_VSC8601,
- &phy_info_VSC8641,
- &phy_info_VSC8221,
- &phy_info_dp83865,
- &phy_info_rtl8211b,
- &phy_info_AR8021,
- &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */
- NULL
-};
-
-/* Grab the identifier of the device's PHY, and search through
- * all of the known PHYs to see if one matches. If so, return
- * it, if not, return NULL
- */
-static struct phy_info *get_phy_info(struct eth_device *dev)
-{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- uint phy_reg, phy_ID;
- int i;
- struct phy_info *theInfo = NULL;
-
- /* Grab the bits from PHYIR1, and put them in the upper half */
- phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
- phy_ID = (phy_reg & 0xffff) << 16;
-
- /* Grab the bits from PHYIR2, and put them in the lower half */
- phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
- phy_ID |= (phy_reg & 0xffff);
-
- /* loop through all the known PHY types, and find one that */
- /* matches the ID we read from the PHY. */
- for (i = 0; phy_info[i]; i++) {
- if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
- theInfo = phy_info[i];
- break;
- }
- }
-
- if (theInfo == &phy_info_generic) {
- printf("%s: No support for PHY id %x; assuming generic\n",
- dev->name, phy_ID);
- } else {
- debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
- }
-
- return theInfo;
-}
-
-/* Execute the given series of commands on the given device's
- * PHY, running functions as necessary
- */
-static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
-{
- int i;
- uint result;
- tsec_mdio_t *phyregs = priv->phyregs;
-
- out_be32(&phyregs->miimcfg, MIIMCFG_RESET);
-
- out_be32(&phyregs->miimcfg, MIIMCFG_INIT_VALUE);
-
- while (in_be32(&phyregs->miimind) & MIIMIND_BUSY)
- ;
-
- for (i = 0; cmd->mii_reg != miim_end; i++) {
- if (cmd->mii_data == miim_read) {
- result = read_phy_reg(priv, cmd->mii_reg);
-
- if (cmd->funct != NULL)
- (*(cmd->funct)) (result, priv);
-
- } else {
- if (cmd->funct != NULL)
- result = (*(cmd->funct)) (cmd->mii_reg, priv);
- else
- result = cmd->mii_data;
-
- write_phy_reg(priv, cmd->mii_reg, result);
-
- }
- cmd++;
- }
-}
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
-
-/*
- * Read a MII PHY register.
- *
- * Returns:
- * 0 on success
- */
-static int tsec_miiphy_read(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
-{
- unsigned short ret;
- struct tsec_private *priv = privlist[0];
-
- if (NULL == priv) {
- printf("Can't read PHY at address %d\n", addr);
- return -1;
- }
-
- ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
- *value = ret;
-
- return 0;
-}
-
-/*
- * Write a MII PHY register.
- *
- * Returns:
- * 0 on success
- */
-static int tsec_miiphy_write(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
-{
- struct tsec_private *priv = privlist[0];
-
- if (NULL == priv) {
- printf("Can't write PHY at address %d\n", addr);
- return -1;
- }
-
- tsec_local_mdio_write(priv->phyregs, addr, reg, value);
-
- return 0;
-}
-
-#endif
-
#ifdef CONFIG_MCAST_TFTP
/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
@@ -1639,14 +189,13 @@ static void init_registers(tsec_t *regs)
/* Configure maccfg2 based on negotiated speed and duplex
* reported by PHY handling code
*/
-static void adjust_link(struct eth_device *dev)
+static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
tsec_t *regs = priv->regs;
u32 ecntrl, maccfg2;
- if (!priv->link) {
- printf("%s: No link.\n", dev->name);
+ if (!phydev->link) {
+ printf("%s: No link.\n", phydev->dev->name);
return;
}
@@ -1657,10 +206,10 @@ static void adjust_link(struct eth_device *dev)
maccfg2 = in_be32(®s->maccfg2);
maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
- if (priv->duplexity)
+ if (phydev->duplex)
maccfg2 |= MACCFG2_FULL_DUPLEX;
- switch (priv->speed) {
+ switch (phydev->speed) {
case 1000:
maccfg2 |= MACCFG2_GMII;
break;
@@ -1671,20 +220,20 @@ static void adjust_link(struct eth_device *dev)
/* Set R100 bit in all modes although
* it is only used in RGMII mode
*/
- if (priv->speed == 100)
+ if (phydev->speed == 100)
ecntrl |= ECNTRL_R100;
break;
default:
- printf("%s: Speed was bad\n", dev->name);
+ printf("%s: Speed was bad\n", phydev->dev->name);
break;
}
out_be32(®s->ecntrl, ecntrl);
out_be32(®s->maccfg2, maccfg2);
- printf("Speed: %d, %s duplex%s\n", priv->speed,
- (priv->duplexity) ? "full" : "half",
- (priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
+ printf("Speed: %d, %s duplex%s\n", phydev->speed,
+ (phydev->duplex) ? "full" : "half",
+ (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
}
/* Set up the buffers and their descriptors, and bring up the
@@ -1696,6 +245,10 @@ static void startup_tsec(struct eth_device *dev)
struct tsec_private *priv = (struct tsec_private *)dev->priv;
tsec_t *regs = priv->regs;
+ /* reset the indices to zero */
+ rxIdx = 0;
+ txIdx = 0;
+
/* Point to the buffer descriptors */
out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx]));
out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
@@ -1716,12 +269,6 @@ static void startup_tsec(struct eth_device *dev)
}
rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
- /* Start up the PHY */
- if (priv->phyinfo)
- phy_run_commands(priv, priv->phyinfo->startup);
-
- adjust_link(dev);
-
/* Enable Transmit and Receive */
setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
@@ -1826,8 +373,7 @@ static void tsec_halt(struct eth_device *dev)
clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
/* Shut down the PHY, as needed */
- if (priv->phyinfo)
- phy_run_commands(priv, priv->phyinfo->shutdown);
+ phy_shutdown(priv->phydev);
}
/* Initializes data structures and registers for the controller,
@@ -1866,20 +412,64 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
out_be32(®s->macstnaddr2, tempval);
- /* reset the indices to zero */
- rxIdx = 0;
- txIdx = 0;
-
/* Clear out (for the most part) the other registers */
init_registers(regs);
/* Ready the device for tx/rx */
startup_tsec(dev);
+ /* Start up the PHY */
+ phy_startup(priv->phydev);
+
+ adjust_link(priv, priv->phydev);
+
/* If there's no link, fail */
- return priv->link ? 0 : -1;
+ return priv->phydev->link ? 0 : -1;
}
+static phy_interface_t tsec_get_interface(struct tsec_private *priv)
+{
+ tsec_t *regs = priv->regs;
+ u32 ecntrl;
+
+ ecntrl = in_be32(®s->ecntrl);
+
+ if (ecntrl & ECNTRL_SGMII_MODE)
+ return PHY_INTERFACE_MODE_SGMII;
+
+ if (ecntrl & ECNTRL_TBI_MODE) {
+ if (ecntrl & ECNTRL_REDUCED_MODE)
+ return PHY_INTERFACE_MODE_RTBI;
+ else
+ return PHY_INTERFACE_MODE_TBI;
+ }
+
+ if (ecntrl & ECNTRL_REDUCED_MODE) {
+ if (ecntrl & ECNTRL_REDUCED_MII_MODE)
+ return PHY_INTERFACE_MODE_RMII;
+ else {
+ phy_interface_t interface = priv->interface;
+
+ /*
+ * This isn't autodetected, so it must
+ * be set by the platform code.
+ */
+ if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
+ (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
+ (interface == PHY_INTERFACE_MODE_RGMII_RXID))
+ return interface;
+
+ return PHY_INTERFACE_MODE_RGMII;
+ }
+ }
+
+ if (priv->flags & TSEC_GIGABIT)
+ return PHY_INTERFACE_MODE_GMII;
+
+ return PHY_INTERFACE_MODE_MII;
+}
+
+
/* Discover which PHY is attached to the device, and configure it
* properly. If the PHY is not recognized, then return 0
* (failure). Otherwise, return 1
@@ -1887,38 +477,32 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
static int init_phy(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
- struct phy_info *curphy;
+ struct phy_device *phydev;
tsec_t *regs = priv->regs;
+ u32 supported = (SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full);
+
+ if (priv->flags & TSEC_GIGABIT)
+ supported |= SUPPORTED_1000baseT_Full;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
- asm("sync");
-
- /* Reset MII (due to new addresses) */
- out_be32(&priv->phyregs->miimcfg, MIIMCFG_RESET);
- asm("sync");
- out_be32(&priv->phyregs->miimcfg, MIIMCFG_INIT_VALUE);
- asm("sync");
- while (in_be32(&priv->phyregs->miimind) & MIIMIND_BUSY)
- ;
- /* Get the cmd structure corresponding to the attached
- * PHY */
- curphy = get_phy_info(dev);
+ priv->interface = tsec_get_interface(priv);
- if (curphy == NULL) {
- priv->phyinfo = NULL;
- printf("%s: No PHY found\n", dev->name);
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII)
+ tsec_configure_serdes(priv);
- return 0;
- }
+ phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
- if (in_be32(®s->ecntrl) & ECNTRL_SGMII_MODE)
- tsec_configure_serdes(priv);
+ phydev->supported &= supported;
+ phydev->advertising = phydev->supported;
- priv->phyinfo = curphy;
+ priv->phydev = phydev;
- phy_run_commands(priv, priv->phyinfo->config);
+ phy_config(phydev);
return 1;
}
@@ -1946,13 +530,14 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
privlist[num_tsecs++] = priv;
priv->regs = tsec_info->regs;
- priv->phyregs = tsec_info->miiregs;
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr;
priv->flags = tsec_info->flags;
sprintf(dev->name, tsec_info->devname);
+ priv->interface = tsec_info->interface;
+ priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
dev->iobase = 0;
dev->priv = priv;
dev->init = tsec_init;
@@ -1974,11 +559,6 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
- miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
-#endif
-
/* Try to initialize PHY here, and return */
return init_phy(dev);
}
@@ -2004,6 +584,13 @@ int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
int tsec_standard_init(bd_t *bis)
{
+ struct fsl_pq_mdio_info info;
+
+ info.regs = (tsec_mii_t *)CONFIG_SYS_MDIO_BASE_ADDR;
+ info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &info);
+
return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
}
new file mode 100644
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Jun-jie Zhang <b18070@freescale.com>
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __FSL_PHY_H__
+#define __FSL_PHY_H__
+
+#include <net.h>
+#include <miiphy.h>
+#include <asm/fsl_enet.h>
+
+/* PHY register offsets */
+#define PHY_EXT_PAGE_ACCESS 0x1f
+
+/* MII Management Configuration Register */
+#define MIIMCFG_RESET_MGMT 0x80000000
+#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
+#define MIIMCFG_INIT_VALUE 0x00000003
+
+/* MII Management Command Register */
+#define MIIMCOM_READ_CYCLE 0x00000001
+#define MIIMCOM_SCAN_CYCLE 0x00000002
+
+/* MII Management Address Register */
+#define MIIMADD_PHY_ADDR_SHIFT 8
+
+/* MII Management Indicator Register */
+#define MIIMIND_BUSY 0x00000001
+#define MIIMIND_NOTVALID 0x00000004
+
+void tsec_local_mdio_write(tsec_mii_t *phyregs, int port_addr, int dev_addr,
+ int reg, int value);
+int tsec_local_mdio_read(tsec_mii_t *phyregs, int port_addr, int dev_addr,
+ int regnum);
+int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
+int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
+ u16 value);
+
+struct fsl_pq_mdio_info {
+ tsec_mii_t *regs;
+ char *name;
+};
+int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
+
+#endif /* __FSL_PHY_H__ */
+
@@ -19,30 +19,36 @@
#include <net.h>
#include <config.h>
+#include <phy.h>
+#include <asm/fsl_enet.h>
#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
+#define CONFIG_SYS_MDIO_BASE_ADDR (TSEC_BASE_ADDR + 0x520)
+
+#define DEFAULT_MII_NAME "FSL_MDIO"
+
#define STD_TSEC_INFO(num) \
{ \
.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
- .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \
- .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
+ .miiregs_sgmii = (tsec_mii_t *)(CONFIG_SYS_MDIO_BASE_ADDR \
+ (num - 1) * TSEC_MDIO_OFFSET), \
.devname = CONFIG_TSEC##num##_NAME, \
.phyaddr = TSEC##num##_PHY_ADDR, \
- .flags = TSEC##num##_FLAGS \
+ .flags = TSEC##num##_FLAGS, \
+ .mii_devname = DEFAULT_MII_NAME \
}
#define SET_STD_TSEC_INFO(x, num) \
{ \
x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
- x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \
- x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
+ x.miiregs_sgmii = (tsec_mii_t *)(CONFIG_SYS_MDIO_BASE_ADDR \
+ (num - 1) * TSEC_MDIO_OFFSET); \
x.devname = CONFIG_TSEC##num##_NAME; \
x.phyaddr = TSEC##num##_PHY_ADDR; \
x.flags = TSEC##num##_FLAGS;\
+ x.mii_devname = DEFAULT_MII_NAME;\
}
#define MAC_ADDR_LEN 6
@@ -51,8 +57,6 @@
#define TSEC_TIMEOUT 1000
#define TOUT_LOOP 1000000
-#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
-
/* TBI register addresses */
#define TBI_CR 0x00
#define TBI_SR 0x01
@@ -96,204 +100,14 @@
#define ECNTRL_INIT_SETTINGS 0x00001000
#define ECNTRL_TBI_MODE 0x00000020
+#define ECNTRL_REDUCED_MODE 0x00000010
#define ECNTRL_R100 0x00000008
+#define ECNTRL_REDUCED_MII_MODE 0x00000004
#define ECNTRL_SGMII_MODE 0x00000002
-#define miim_end -2
-#define miim_read -1
-
#ifndef CONFIG_SYS_TBIPA_VALUE
#define CONFIG_SYS_TBIPA_VALUE 0x1f
#endif
-#define MIIMCFG_INIT_VALUE 0x00000003
-#define MIIMCFG_RESET 0x80000000
-
-#define MIIMIND_BUSY 0x00000001
-#define MIIMIND_NOTVALID 0x00000004
-
-#define MIIM_CONTROL 0x00
-#define MIIM_CONTROL_RESET 0x00009140
-#define MIIM_CONTROL_INIT 0x00001140
-#define MIIM_CONTROL_RESTART 0x00001340
-#define MIIM_ANEN 0x00001000
-
-#define MIIM_CR 0x00
-#define MIIM_CR_RST 0x00008000
-#define MIIM_CR_INIT 0x00001000
-
-#define MIIM_STATUS 0x1
-#define MIIM_STATUS_AN_DONE 0x00000020
-#define MIIM_STATUS_LINK 0x0004
-
-#define MIIM_PHYIR1 0x2
-#define MIIM_PHYIR2 0x3
-
-#define MIIM_ANAR 0x4
-#define MIIM_ANAR_INIT 0x1e1
-
-#define MIIM_TBI_ANLPBPA 0x5
-#define MIIM_TBI_ANLPBPA_HALF 0x00000040
-#define MIIM_TBI_ANLPBPA_FULL 0x00000020
-
-#define MIIM_TBI_ANEX 0x6
-#define MIIM_TBI_ANEX_NP 0x00000004
-#define MIIM_TBI_ANEX_PRX 0x00000002
-
-#define MIIM_GBIT_CONTROL 0x9
-#define MIIM_GBIT_CONTROL_INIT 0xe00
-
-#define MIIM_EXT_PAGE_ACCESS 0x1f
-
-/* Broadcom BCM54xx -- taken from linux sungem_phy */
-#define MIIM_BCM54xx_AUXCNTL 0x18
-#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) ((val & 0x7) << 12)|(val & 0x7)
-#define MIIM_BCM54xx_AUXSTATUS 0x19
-#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
-#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
-
-#define MIIM_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
-#define MIIM_BCM54XX_SHD_WRITE 0x8000
-#define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
-#define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
-#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \
- (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
- MIIM_BCM54XX_SHD_DATA(data))
-
-#define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
-#define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
-#define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
-#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
-
-/* Cicada Auxiliary Control/Status Register */
-#define MIIM_CIS8201_AUX_CONSTAT 0x1c
-#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
-#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
-#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
-#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
-#define MIIM_CIS8201_AUXCONSTAT_100 0x0008
-
-/* Cicada Extended Control Register 1 */
-#define MIIM_CIS8201_EXT_CON1 0x17
-#define MIIM_CIS8201_EXTCON1_INIT 0x0000
-
-/* Cicada 8204 Extended PHY Control Register 1 */
-#define MIIM_CIS8204_EPHY_CON 0x17
-#define MIIM_CIS8204_EPHYCON_INIT 0x0006
-#define MIIM_CIS8204_EPHYCON_RGMII 0x1100
-
-/* Cicada 8204 Serial LED Control Register */
-#define MIIM_CIS8204_SLED_CON 0x1b
-#define MIIM_CIS8204_SLEDCON_INIT 0x1115
-
-#define MIIM_GBIT_CON 0x09
-#define MIIM_GBIT_CON_ADVERT 0x0e00
-
-/* Entry for Vitesse VSC8244 regs starts here */
-/* Vitesse VSC8244 Auxiliary Control/Status Register */
-#define MIIM_VSC8244_AUX_CONSTAT 0x1c
-#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
-#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
-#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
-#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
-#define MIIM_VSC8244_AUXCONSTAT_100 0x0008
-#define MIIM_CONTROL_INIT_LOOPBACK 0x4000
-
-/* Vitesse VSC8244 Extended PHY Control Register 1 */
-#define MIIM_VSC8244_EPHY_CON 0x17
-#define MIIM_VSC8244_EPHYCON_INIT 0x0006
-
-/* Vitesse VSC8244 Serial LED Control Register */
-#define MIIM_VSC8244_LED_CON 0x1b
-#define MIIM_VSC8244_LEDCON_INIT 0xF011
-
-/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
-/* Vitesse VSC8601 Extended PHY Control Register 1 */
-#define MIIM_VSC8601_EPHY_CON 0x17
-#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
-#define MIIM_VSC8601_SKEW_CTRL 0x1c
-
-/* 88E1011 PHY Status Register */
-#define MIIM_88E1011_PHY_STATUS 0x11
-#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
-#define MIIM_88E1011_PHYSTAT_GBIT 0x8000
-#define MIIM_88E1011_PHYSTAT_100 0x4000
-#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
-#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
-#define MIIM_88E1011_PHYSTAT_LINK 0x0400
-
-#define MIIM_88E1011_PHY_SCR 0x10
-#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
-
-/* 88E1111 PHY LED Control Register */
-#define MIIM_88E1111_PHY_LED_CONTROL 24
-#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
-#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
-
-/* 88E1121 PHY LED Control Register */
-#define MIIM_88E1121_PHY_LED_CTRL 16
-#define MIIM_88E1121_PHY_LED_PAGE 3
-#define MIIM_88E1121_PHY_LED_DEF 0x0030
-
-/* 88E1121 PHY IRQ Enable/Status Register */
-#define MIIM_88E1121_PHY_IRQ_EN 18
-#define MIIM_88E1121_PHY_IRQ_STATUS 19
-
-#define MIIM_88E1121_PHY_PAGE 22
-
-/* 88E1145 Extended PHY Specific Control Register */
-#define MIIM_88E1145_PHY_EXT_CR 20
-#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
-#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
-
-#define MIIM_88E1145_PHY_PAGE 29
-#define MIIM_88E1145_PHY_CAL_OV 30
-
-/* RTL8211B PHY Status Register */
-#define MIIM_RTL8211B_PHY_STATUS 0x11
-#define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000
-#define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000
-#define MIIM_RTL8211B_PHYSTAT_100 0x4000
-#define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000
-#define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800
-#define MIIM_RTL8211B_PHYSTAT_LINK 0x0400
-
-/* DM9161 Control register values */
-#define MIIM_DM9161_CR_STOP 0x0400
-#define MIIM_DM9161_CR_RSTAN 0x1200
-
-#define MIIM_DM9161_SCR 0x10
-#define MIIM_DM9161_SCR_INIT 0x0610
-
-/* DM9161 Specified Configuration and Status Register */
-#define MIIM_DM9161_SCSR 0x11
-#define MIIM_DM9161_SCSR_100F 0x8000
-#define MIIM_DM9161_SCSR_100H 0x4000
-#define MIIM_DM9161_SCSR_10F 0x2000
-#define MIIM_DM9161_SCSR_10H 0x1000
-
-/* DM9161 10BT Configuration/Status */
-#define MIIM_DM9161_10BTCSR 0x12
-#define MIIM_DM9161_10BTCSR_INIT 0x7800
-
-/* LXT971 Status 2 registers */
-#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
-#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
-#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
-#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
-
-/* DP83865 Control register values */
-#define MIIM_DP83865_CR_INIT 0x9200
-
-/* DP83865 Link and Auto-Neg Status Register */
-#define MIIM_DP83865_LANR 0x11
-#define MIIM_DP83865_SPD_MASK 0x0018
-#define MIIM_DP83865_SPD_1000 0x0010
-#define MIIM_DP83865_SPD_100 0x0008
-#define MIIM_DP83865_DPX_FULL 0x0002
-
-#define MIIM_READ_COMMAND 0x00000001
#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
@@ -467,22 +281,6 @@ typedef struct tsec_hash_regs
uint res2[24];
} tsec_hash_t;
-typedef struct tsec_mdio {
- uint res1[4];
- uint ieventm;
- uint imaskm;
- uint res2;
- uint emapm;
- uint res3[320];
- uint miimcfg; /* MII Management: Configuration */
- uint miimcom; /* MII Management: Command */
- uint miimadd; /* MII Management: Address */
- uint miimcon; /* MII Management: Control */
- uint miimstat; /* MII Management: Status */
- uint miimind; /* MII Management: Indicators */
- uint res4[690];
-} tsec_mdio_t;
-
typedef struct tsec
{
/* General Control and Status Registers (0x2_n000) */
@@ -578,79 +376,29 @@ typedef struct tsec
uint resc00[256];
} tsec_t;
-#define TSEC_GIGABIT (1)
+#define TSEC_GIGABIT (1 << 0)
-/* This flag currently only has
- * meaning if we're using the eTSEC */
+/* These flags currently only have meaning if we're using the eTSEC */
#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
-#define TSEC_FIBER (1 << 3) /* PHY uses fiber, eg 1000 Base-X */
struct tsec_private {
tsec_t *regs;
- tsec_mdio_t *phyregs;
- tsec_mdio_t *phyregs_sgmii;
- struct phy_info *phyinfo;
+ tsec_mii_t *phyregs_sgmii;
+ struct phy_device *phydev;
+ phy_interface_t interface;
+ struct mii_dev *bus;
uint phyaddr;
+ char mii_devname[16];
u32 flags;
- uint link;
- uint duplexity;
- uint speed;
-};
-
-
-/*
- * struct phy_cmd: A command for reading or writing a PHY register
- *
- * mii_reg: The register to read or write
- *
- * mii_data: For writes, the value to put in the register.
- * A value of -1 indicates this is a read.
- *
- * funct: A function pointer which is invoked for each command.
- * For reads, this function will be passed the value read
- * from the PHY, and process it.
- * For writes, the result of this function will be written
- * to the PHY register
- */
-struct phy_cmd {
- uint mii_reg;
- uint mii_data;
- uint (*funct) (uint mii_reg, struct tsec_private * priv);
-};
-
-/* struct phy_info: a structure which defines attributes for a PHY
- *
- * id will contain a number which represents the PHY. During
- * startup, the driver will poll the PHY to find out what its
- * UID--as defined by registers 2 and 3--is. The 32-bit result
- * gotten from the PHY will be shifted right by "shift" bits to
- * discard any bits which may change based on revision numbers
- * unimportant to functionality
- *
- * The struct phy_cmd entries represent pointers to an arrays of
- * commands which tell the driver what to do to the PHY.
- */
-struct phy_info {
- uint id;
- char *name;
- uint shift;
- /* Called to configure the PHY, and modify the controller
- * based on the results */
- struct phy_cmd *config;
-
- /* Called when starting up the controller */
- struct phy_cmd *startup;
-
- /* Called when bringing down the controller */
- struct phy_cmd *shutdown;
};
struct tsec_info_struct {
tsec_t *regs;
- tsec_mdio_t *miiregs;
- tsec_mdio_t *miiregs_sgmii;
+ tsec_mii_t *miiregs_sgmii;
char *devname;
+ char *mii_devname;
+ phy_interface_t interface;
unsigned int phyaddr;
u32 flags;
};