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[U-Boot,v2,1/5] sunxi: R40: add gigabit ethernet clocks

Message ID 20180417134235.10502-1-lothar.felten@gmail.com
State Changes Requested
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series [U-Boot,v2,1/5] sunxi: R40: add gigabit ethernet clocks | expand

Commit Message

Lothar Felten April 17, 2018, 1:42 p.m. UTC 
Add clock control entries for the gigabit interface of the Allwinner
R40/V40 CPU

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

Comments

Maxime Ripard April 19, 2018, 8:34 a.m. UTC | #1 
On Tue, Apr 17, 2018 at 03:42:31PM +0200, Lothar Felten wrote:
> Add clock control entries for the gigabit interface of the Allwinner
> R40/V40 CPU
> 
> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d35aa479f7..3ea473c302 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -61,7 +61,11 @@  struct sunxi_ccm_reg {
 	u32 reserved11;
 	u32 sata_clk_cfg;	/* 0xc8 SATA clock control (R40 only) */
 	u32 usb_clk_cfg;	/* 0xcc USB clock control */
-	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control */
+#ifdef CONFIG_MACH_SUN8I_R40
+	u32 cir0_clk_cfg;	/* 0xd0 CIR0 clock control (R40 only) */
+#else
+	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control (not for R40) */
+#endif
 	u32 reserved12[7];
 	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
 	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
@@ -104,7 +108,11 @@  struct sunxi_ccm_reg {
 	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
 	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
 	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
+#ifdef CONFIG_MACH_SUN8I_R40
+	u32 gmac_clk_cfg;	/* 0x164 GMAC clock control (R40 only) */
+#else
 	u32 reserved16;
+#endif
 	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
 	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
 	u32 reserved17[4];