From patchwork Tue Apr 17 03:43:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moritz Fischer X-Patchwork-Id: 899048 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40QB3G2CNzz9s1B for ; Tue, 17 Apr 2018 13:45:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752326AbeDQDof (ORCPT ); Mon, 16 Apr 2018 23:44:35 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:33463 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752145AbeDQDod (ORCPT ); Mon, 16 Apr 2018 23:44:33 -0400 Received: by mail-pg0-f68.google.com with SMTP id i194so4786183pgd.0 for ; Mon, 16 Apr 2018 20:44:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eEDwFpf+d22NSlATwj98p3oHlhm5buFo6ft3FtCiemo=; b=HTJHQVslET+zEtevOHzozPA2wwhiAdGFumDfmYwFgDmDROmpITfGsk5z9y0JBuugw8 voz8axh4yZU6WBPCLFWrgVAUsSGNOw25LasK/Kg7DJ5GXB+Mbv9opofbWmNQJqEkYh3H Bf4FgR431PaHYHPuTuPdUi/vKqwdkN0gtkmX9n0YoO/5KyP2O27KQ5UXPZHdLOE1zizf 9lKdH71bgWPHN0si4OOufP1xchOqLoog8aaVKDHuKYUTEI8UBiQL6PlrOvUIMXdxj4IA DKBIUlxpR4WrtwkxyDKXwmj3mMZ7ZvXkJs2LcSKlUVp9EuHQa1PY//UpKnBb3QDwYC/d 9Bog== X-Gm-Message-State: ALQs6tCuCXQ95d38329lWItiIzC+p02rO76hfYoNDwjQtNsQxNspTuyt nkFg/nMQzWvIX2FUl0P/BWT2SQ== X-Google-Smtp-Source: AIpwx48MnwI5Z71el9Fe9qCxhggL1Szu+BVS1HbvmuWNQiX0hpwc14mdFZogSBmA0+oj4zkPseqR/Q== X-Received: by 10.98.70.8 with SMTP id t8mr440189pfa.185.1523936672935; Mon, 16 Apr 2018 20:44:32 -0700 (PDT) Received: from localhost (c-107-3-165-230.hsd1.ca.comcast.net. [107.3.165.230]) by smtp.gmail.com with ESMTPSA id p6sm11977042pfn.140.2018.04.16.20.44.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Apr 2018 20:44:32 -0700 (PDT) From: Moritz Fischer To: gregkh@linux-foundation.org Cc: linux-fpga.vger@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, atull@kernel.org, robh+dt@kernel.org, Paolo Pisati , Moritz Fischer Subject: [PATCH 1/3] dt: bindings: fpga: add lattice machxo2 slave spi binding description Date: Mon, 16 Apr 2018 20:43:35 -0700 Message-Id: <20180417034337.8855-2-mdf@kernel.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180417034337.8855-1-mdf@kernel.org> References: <20180417034337.8855-1-mdf@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Paolo Pisati Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface. Signed-off-by: Paolo Pisati Acked-by: Rob Herring Acked-by: Alan Tull Signed-off-by: Moritz Fischer --- .../bindings/fpga/lattice-machxo2-spi.txt | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file mode 100644 index 000000000000..a8c362eb160c --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt @@ -0,0 +1,29 @@ +Lattice MachXO2 Slave SPI FPGA Manager + +Lattice MachXO2 FPGAs support a method of loading the bitstream over +'slave SPI' interface. + +See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com + +Required properties: +- compatible: should contain "lattice,machxo2-slave-spi" +- reg: spi chip select of the FPGA + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr_spi>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + spi1: spi@2000 { + ... + + fpga_mgr_spi: fpga-mgr@0 { + compatible = "lattice,machxo2-slave-spi"; + spi-max-frequency = <8000000>; + reg = <0>; + }; + };