@@ -1019,10 +1019,9 @@ static int handle_all_core_tfac_error(uint64_t tfmr, uint64_t *out_flags)
hmi_rendez_vous(2);
/* We can now clear the error conditions in the core. */
- if (!tfmr_clear_core_errors(tfmr)) {
- recover = 0;
+ recover = tfmr_clear_core_errors(tfmr);
+ if (recover == 0)
goto error_out;
- }
/* Third rendez-vous. We could in theory do the timebase resync as
* part of the previous one, but I prefer having all the error
@@ -1491,18 +1491,21 @@ void tfmr_cleanup_core_errors(uint64_t tfmr)
}
}
-bool tfmr_clear_core_errors(uint64_t tfmr)
+int tfmr_clear_core_errors(uint64_t tfmr)
{
uint64_t tfmr_reset_errors = 0;
- if (tfmr & SPR_TFMR_HDEC_PARITY_ERROR)
- tfmr_reset_errors |= SPR_TFMR_HDEC_PARITY_ERROR;
+ /* return -1 if there is nothing to be fixed. */
+ if (!(tfmr & SPR_TFMR_HDEC_PARITY_ERROR))
+ return -1;
+
+ tfmr_reset_errors |= SPR_TFMR_HDEC_PARITY_ERROR;
/* Write TFMR twice to clear the error */
mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors);
mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors);
- return true;
+ return 1;
}
/*
@@ -33,7 +33,7 @@ extern int chiptod_recover_tb_errors(bool *out_resynced);
extern bool tfmr_recover_local_errors(uint64_t tfmr);
extern bool recover_corrupt_tfmr(void);
extern void tfmr_cleanup_core_errors(uint64_t tfmr);
-extern bool tfmr_clear_core_errors(uint64_t tfmr);
+extern int tfmr_clear_core_errors(uint64_t tfmr);
extern void chiptod_reset_tb(void);
extern bool chiptod_adjust_topology(enum chiptod_topology topo, bool enable);
extern bool chiptod_capp_timebase_sync(unsigned int chip_id, uint32_t tfmr_addr,