From patchwork Mon Apr 16 04:32:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 898453 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KBdyZulY"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40Pb8x14wfz9s21 for ; Mon, 16 Apr 2018 14:33:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752841AbeDPEdE (ORCPT ); Mon, 16 Apr 2018 00:33:04 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:38663 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751113AbeDPEdD (ORCPT ); Mon, 16 Apr 2018 00:33:03 -0400 Received: by mail-pl0-f66.google.com with SMTP id c7-v6so9313738plr.5 for ; Sun, 15 Apr 2018 21:33:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vdE1j1c4PH4zcKSRRFNdK9lUI78hS+IfpeavSoAgqxA=; b=KBdyZulYjoHaM8oISxPZ3K/KhrbSxeofEToTWZqwgsZJHdtGpctWXIhCStbo/NmoM7 lu9OAXVRd/yPlNm8FmYRpLF8iC7RJSRq6JmA7WyYn5CDIud8oeMemFlidBugLUArNGOi Ly8OWgBUjkI8F4R3d+oWgqvGk0J+sgnI5IM49y0rsGD9Fs5T2siSE4M69p/YjhQbO5RZ EIAIsBKMcOnjTZ+iqj5wNArXcyD6wDDAXdY7sfcTCor3+AU3UHzVD/rOy0lYgVU46zRh ul8dzq5iN+8zo+pokOEMSiufe2d7oxLvb6h3Bf5oI4C98vimLIlUvZWbeHztE7TBjfZu 3Aww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vdE1j1c4PH4zcKSRRFNdK9lUI78hS+IfpeavSoAgqxA=; b=YcTblG5Omdrux2JQUcaa1FXP44LKKNrs8VAJXcHu3Vh5v5TxwgbUBA4iFkguqB6Zsy YaVFIQWlui0sgNS4ufMejMh2rjqHDfq0ZvAcS1sy1Cvdv2JinNKGxb9GQkWYxs/gTsgY To3C/Q1+UzwJl2RZIdOx8UHqPP/NxC4bC88UPr9FuE490SGlcdDfXHQGVP8PjMWSCn7y VN8Ol9hvkrjm2oIZiIgj/Up/fdPGYEv519QTnEquUbTgwpbq1kykNty0lPI2Py6mZB5/ GeCsX6AgyvNPtGR38u09zFtwCxo5LK4bDvKsjfvGh1KiXghReRKhqCk2u8/ubFYlu5YC YvXA== X-Gm-Message-State: ALQs6tA48LzSihwoj2jKCiE+CGvV029NYUaw1f8VDsp0aVdmHoBPY5U9 OeoWn1St2S3/577739KzJBPbtA== X-Google-Smtp-Source: AIpwx4+Pzt7V1f84gr+TyekNcreZ96EgIclH+v/XiPuwZc1xOHFEB4MbSKQKw2kncKdIVnWtSZ0rbA== X-Received: by 2002:a17:902:8d98:: with SMTP id v24-v6mr3574642plo.146.1523853182887; Sun, 15 Apr 2018 21:33:02 -0700 (PDT) Received: from roar.au.ibm.com (59-102-70-78.tpgi.com.au. [59.102.70.78]) by smtp.gmail.com with ESMTPSA id e87sm23029614pfd.136.2018.04.15.21.33.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 15 Apr 2018 21:33:02 -0700 (PDT) From: Nicholas Piggin To: kvm-ppc@vger.kernel.org Cc: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org Subject: [PATCH v2 4/5] KVM: PPC: Book3S HV: radix handle process scoped LPID flush in C, with relocation on Date: Mon, 16 Apr 2018 14:32:39 +1000 Message-Id: <20180416043240.8796-5-npiggin@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180416043240.8796-1-npiggin@gmail.com> References: <20180416043240.8796-1-npiggin@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org The radix guest code can has fewer restrictions about what context it can run in, so move this flushing out of assembly and have it use the Linux TLB flush implementations introduced previously. This allows powerpc:tlbie trace events to be used. This changes the tlbiel sequence to only execute RIC=2 flush once on the first set flushed, which matches the rest of the Linux flushing. This does not change semantics of the flush. Signed-off-by: Nicholas Piggin --- arch/powerpc/kvm/book3s_hv.c | 26 +++++++++++++++++++++++++ arch/powerpc/kvm/book3s_hv_rmhandlers.S | 13 ++++++------- 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 81e2ea882d97..c1660df41190 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -2901,6 +2901,32 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc) for (sub = 0; sub < core_info.n_subcores; ++sub) spin_unlock(&core_info.vc[sub]->lock); + if (kvm_is_radix(vc->kvm)) { + int tmp = pcpu; + + /* + * Do we need to flush the process scoped TLB for the LPAR? + * + * On POWER9, individual threads can come in here, but the + * TLB is shared between the 4 threads in a core, hence + * invalidating on one thread invalidates for all. + * Thus we make all 4 threads use the same bit here. + * + * Hash must be flushed in realmode in order to use tlbiel. + */ + mtspr(SPRN_LPID, vc->kvm->arch.lpid); + isync(); + + if (cpu_has_feature(CPU_FTR_ARCH_300)) + tmp &= ~0x3UL; + + if (cpumask_test_cpu(tmp, &vc->kvm->arch.need_tlb_flush)) { + radix__local_flush_tlb_lpid_guest(vc->kvm->arch.lpid); + /* Clear the bit after the TLB flush */ + cpumask_clear_cpu(tmp, &vc->kvm->arch.need_tlb_flush); + } + } + /* * Interrupts will be enabled once we get into the guest, * so tell lockdep that we're about to enable interrupts. diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index bd63fa8a08b5..d4c7bb3e777e 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -636,6 +636,10 @@ kvmppc_hv_entry: /* Primary thread switches to guest partition. */ cmpwi r6,0 bne 10f + + /* Radix has already switched LPID and flushed core TLB */ + bne cr7,22f + lwz r7,KVM_LPID(r9) BEGIN_FTR_SECTION ld r6,KVM_SDR1(r9) @@ -647,7 +651,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) mtspr SPRN_LPID,r7 isync - /* See if we need to flush the TLB */ + /* See if we need to flush the TLB. Hash has to be done in RM */ lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */ BEGIN_FTR_SECTION /* @@ -674,15 +678,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) li r7,0x800 /* IS field = 0b10 */ ptesync li r0,0 /* RS for P9 version of tlbiel */ - bne cr7, 29f 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */ addi r7,r7,0x1000 bdnz 28b - b 30f -29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */ - addi r7,r7,0x1000 - bdnz 29b -30: ptesync + ptesync 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */ andc r7,r7,r8 stdcx. r7,0,r6