From patchwork Fri Apr 13 18:29:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 898077 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=cogentembedded.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=cogentembedded-com.20150623.gappssmtp.com header.i=@cogentembedded-com.20150623.gappssmtp.com header.b="yxWpzVGy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40N5sd0NYpz9rvt for ; Sat, 14 Apr 2018 04:29:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751109AbeDMS3j (ORCPT ); Fri, 13 Apr 2018 14:29:39 -0400 Received: from mail-lf0-f66.google.com ([209.85.215.66]:36658 "EHLO mail-lf0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751036AbeDMS3i (ORCPT ); Fri, 13 Apr 2018 14:29:38 -0400 Received: by mail-lf0-f66.google.com with SMTP id d20-v6so13878783lfe.3 for ; Fri, 13 Apr 2018 11:29:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:subject:to:cc:references:organization:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=C6cHNAa3wReEY68z6mpXEPFmdTHkaEqIrf/rwFdTsxk=; b=yxWpzVGy304bjIMYxm8XhlQrYB/fZdmBDFF60fJVnDRU+RZtEZV0V7ZSRMww/tmZLd ZjHa5Phnr/9k3+zDkiWrj96ITcCpYL6qSUKOtz2iZb2534uAGsW3hk0JcImACIwa3Ivk gHXFiKLlgrne5yxHn21Cg0B/NyHaKAv8AxewSYhP4lBUo8jHhljWQKwakVsYb953h8WN WCXIEuKz+E3bz+7dlFYHRPzeFYeL48KyV9TUgDwGBdmFTvZ8ugfUe14jNmQdjj1FfMC/ SZ4i/ksoJhJ9i4lSQiUXo4vp7KywwbrC5OUd43wOiMCqJ3MNuYWaMpzPc0tJHB88IG0Q uc+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=C6cHNAa3wReEY68z6mpXEPFmdTHkaEqIrf/rwFdTsxk=; b=sWVojl1BBFN0Ce/+3EfvN7DmEtiq1bBJiYwqWN+WxFp51b7HRNSpzCVh3rfEiR/AvR X2yzUKRw3SpIcGAO85IbXfH01MAWjOA0TAMgJkj1Hs0acpiWXCo9+ikc7CcABS5N52M2 DumDSdC4Lms9rxu9AvTkxRDfbHZG71R1YUntPuqzXjmQ0PWhrU2W0YLPMP7zIOgCtqQq KfOGNb/fJ7ttX8RNrhbSamkkORZON1/AlrJyMRXJwYWAm8VUiRHH7GdGBzQIWROGp9Ey cceyPwws0JbL01vAfTMdrQywFflgsBua1Fy8tIC0ynq/lcO2NI9nIGDl/do3ydL7N0/Y 24pw== X-Gm-Message-State: ALQs6tDNxqlhFqolDUBy+cVRzX1Nny4iilUuVcec/EGszDI1oUHUVku/ opsPw7OgU3eNag/cfdizgOlDWQ== X-Google-Smtp-Source: AIpwx4+dwZ31RxWY7Xc54nKMhbADAqzVtA0gto18PVYgGXN/jSrE7SHWu5Teee+R8R+hNhgtg6+exg== X-Received: by 10.46.25.28 with SMTP id p28mr3864518lje.127.1523644177313; Fri, 13 Apr 2018 11:29:37 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.80.168]) by smtp.gmail.com with ESMTPSA id t66-v6sm1349148lff.40.2018.04.13.11.29.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Apr 2018 11:29:36 -0700 (PDT) From: Sergei Shtylyov Subject: [PATCH] pinctrl: sh-pfc: r8a77970: add pin I/O voltage control To: Linus Walleij , Geert Uytterhoeven , linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Laurent Pinchart References: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Organization: Cogent Embedded Message-ID: <1c6cc202-5f20-4304-11ae-79ea0c559457@cogentembedded.com> Date: Fri, 13 Apr 2018 21:29:33 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Content-Language: en-MW Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the pin I/O voltage level control to the R8A77980 PFC driver. Loosely based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77980.c | 50 +++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77980.c =================================================================== --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77980.c +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77980.c @@ -19,10 +19,10 @@ #include "sh_pfc.h" #define CPU_ALL_PORT(fn, sfx) \ - PORT_GP_22(0, fn, sfx), \ + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_28(1, fn, sfx), \ - PORT_GP_30(2, fn, sfx), \ - PORT_GP_17(3, fn, sfx), \ + PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_25(4, fn, sfx), \ PORT_GP_15(5, fn, sfx) @@ -2779,8 +2779,51 @@ static const struct pinmux_cfg_reg pinmu { }, }; +enum ioctrl_regs { + IOCTRL30, + IOCTRL31, + IOCTRL32, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [IOCTRL30] = { 0xe6060380, }, + [IOCTRL31] = { 0xe6060384, }, + [IOCTRL32] = { 0xe6060388, }, + { /* sentinel */ }, +}; + +static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) +{ + int bit = pin & 0x1f; + + *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; + if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) + return bit; + else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) + return bit + 22; + + *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg; + if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) + return bit - 10; + if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) || + (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))) + return bit + 7; + + *pocctrl = pinmux_ioctrl_regs[IOCTRL32].reg; + if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29)) + return pin - 25; + + return -EINVAL; +} + +static const struct sh_pfc_soc_operations pinmux_ops = { + .pin_to_pocctrl = r8a77980_pin_to_pocctrl, +}; + const struct sh_pfc_soc_info r8a77980_pinmux_info = { .name = "r8a77980_pfc", + .ops = &pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -2793,6 +2836,7 @@ const struct sh_pfc_soc_info r8a77980_pi .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data),