From patchwork Thu Apr 12 22:12:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Gorinov X-Patchwork-Id: 897812 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40Mb4g6HnTz9s0R for ; Fri, 13 Apr 2018 08:22:27 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 601FAC21DF3; Thu, 12 Apr 2018 22:21:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BBF33C21DAF; Thu, 12 Apr 2018 22:21:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9401BC21C2F; Thu, 12 Apr 2018 22:20:45 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lists.denx.de (Postfix) with ESMTPS id 2C76BC21D9A for ; Thu, 12 Apr 2018 22:20:42 +0000 (UTC) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2018 15:20:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,443,1517904000"; d="scan'208";a="33267886" Received: from dph9ls1.fm.intel.com (HELO intel.com) ([10.80.209.182]) by orsmga008.jf.intel.com with ESMTP; 12 Apr 2018 15:20:37 -0700 Date: Thu, 12 Apr 2018 15:12:08 -0700 From: Ivan Gorinov To: u-boot@lists.denx.de Message-ID: <269698c303c3da454b34f149d4a3562fc57091f2.1523570597.git.ivan.gorinov@intel.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Cc: Andy Shevchenko Subject: [U-Boot] [PATCH v6 1/2] x86: Add TSC-specific timer functions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Coreboot timestamp functions and Quark memory reference code use get_tbclk() to get TSC frequency. This will not work if another early timer is selected. Add tsc_rate_mhz() function and use it in the code that specifically needs to get TSC rate regardless of currently selected early timer. Signed-off-by: Ivan Gorinov --- arch/x86/cpu/coreboot/timestamp.c | 2 +- arch/x86/cpu/quark/mrc_util.c | 13 ++++++------- arch/x86/include/asm/u-boot-x86.h | 2 +- drivers/timer/tsc_timer.c | 33 ++++++++++++++++++++++++--------- 4 files changed, 32 insertions(+), 18 deletions(-) diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c index b382795..05bb214 100644 --- a/arch/x86/cpu/coreboot/timestamp.c +++ b/arch/x86/cpu/coreboot/timestamp.c @@ -78,7 +78,7 @@ int timestamp_add_to_bootstage(void) if (name) { bootstage_add_record(0, name, BOOTSTAGEF_ALLOC, tse->entry_stamp / - get_tbclk_mhz()); + tsc_rate_mhz()); } } diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index fac2d72..4794395 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -57,19 +57,18 @@ void mrc_post_code(uint8_t major, uint8_t minor) void delay_n(uint32_t ns) { /* 1000 MHz clock has 1ns period --> no conversion required */ - uint64_t final_tsc = rdtsc(); + uint64_t start_tsc = rdtsc(); + uint64_t ticks; - final_tsc += ((get_tbclk_mhz() * ns) / 1000); - - while (rdtsc() < final_tsc) - ; + ticks = (tsc_rate_mhz() * ns) / 1000; + while (rdtsc() - start_tsc < ticks); } /* Delay number of microseconds */ -void delay_u(uint32_t ms) +void delay_u(uint32_t us) { /* 64-bit math is not an option, just use loops */ - while (ms--) + while (us--) delay_n(1000); } diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 187fe5f..de68120 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -29,7 +29,7 @@ int cleanup_before_linux(void); void timer_isr(void *); typedef void (timer_fnc_t) (void); int register_timer_isr (timer_fnc_t *isr_func); -unsigned long get_tbclk_mhz(void); +unsigned long tsc_rate_mhz(void); void timer_set_base(uint64_t base); int i8254_init(void); diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 9296de6..98cbf12 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -277,15 +277,12 @@ success: return delta / 1000; } -/* Get the speed of the TSC timer in MHz */ -unsigned notrace long get_tbclk_mhz(void) -{ - return get_tbclk() / 1000000; -} - static ulong get_ms_timer(void) { - return (get_ticks() * 1000) / get_tbclk(); + if (gd->arch.clock_rate == 0) + return 0; + + return (rdtsc() * 1000) / gd->arch.clock_rate; } ulong get_timer(ulong base) @@ -295,7 +292,10 @@ ulong get_timer(ulong base) ulong notrace timer_get_us(void) { - return get_ticks() / get_tbclk_mhz(); + if (gd->arch.clock_rate == 0) + return 0; + + return (rdtsc() * 1000000) / gd->arch.clock_rate; } ulong timer_get_boot_us(void) @@ -308,7 +308,7 @@ void __udelay(unsigned long usec) u64 now = get_ticks(); u64 stop; - stop = now + usec * get_tbclk_mhz(); + stop = now + ((u64)usec * gd->arch.clock_rate) / 1000000; while ((int64_t)(stop - get_ticks()) > 0) #if defined(CONFIG_QEMU) && defined(CONFIG_SMP) @@ -355,6 +355,14 @@ static void tsc_timer_ensure_setup(void) } } +/* Get the speed of the TSC timer in MHz */ +unsigned notrace long tsc_rate_mhz(void) +{ + tsc_timer_ensure_setup(); + + return gd->arch.clock_rate / 1000000; +} + static int tsc_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); @@ -365,6 +373,13 @@ static int tsc_timer_probe(struct udevice *dev) return 0; } +int timer_init(void) +{ + tsc_timer_ensure_setup(); + + return 0; +} + unsigned long notrace timer_early_get_rate(void) { tsc_timer_ensure_setup();