From patchwork Thu Apr 12 12:45:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 897643 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40MLJc17Y7z9s2M for ; Thu, 12 Apr 2018 22:46:56 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40MLJb6qKqzDqhm for ; Thu, 12 Apr 2018 22:46:55 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40MLH81RbfzF1Rc for ; Thu, 12 Apr 2018 22:45:39 +1000 (AEST) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w3CCdRXU016105 for ; Thu, 12 Apr 2018 08:45:37 -0400 Received: from e06smtp10.uk.ibm.com (e06smtp10.uk.ibm.com [195.75.94.106]) by mx0b-001b2d01.pphosted.com with ESMTP id 2ha5x8w91s-1 (version=TLSv1.2 cipher=AES256-SHA256 bits=256 verify=NOT) for ; Thu, 12 Apr 2018 08:45:36 -0400 Received: from localhost by e06smtp10.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 12 Apr 2018 13:45:33 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w3CCjWFr59834592; Thu, 12 Apr 2018 12:45:32 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 56BF352049; Thu, 12 Apr 2018 12:36:28 +0100 (BST) Received: from borneo.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.34]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 2D71452045; Thu, 12 Apr 2018 12:36:28 +0100 (BST) From: Frederic Barrat To: andrew.donnellan@au1.ibm.com, skiboot@lists.ozlabs.org Date: Thu, 12 Apr 2018 14:45:25 +0200 X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180412124526.12662-1-fbarrat@linux.ibm.com> References: <20180412124526.12662-1-fbarrat@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18041212-0040-0000-0000-0000042D845F X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18041212-0041-0000-0000-000026319D3B Message-Id: <20180412124526.12662-5-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-04-12_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1804120127 Subject: [Skiboot] [PATCH 4/5] npu2-opencapi: Cleanup traces printed during link training X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Frederic Barrat Now that links may train in parallel, traces shown during training can be all mixed up. So add a prefix to all the traces to clearly identify the chip and link the trace refers to: OCAPI[:]: this is a very useful message The lower-level hardware procedures (npu2-hw-procedures.c) also print traces which would need work. But that code is being reworked to be better integrated with opencapi and nvidia, so leave it alone for now. Signed-off-by: Frederic Barrat Acked-by: Andrew Donnellan --- hw/npu2-opencapi.c | 76 ++++++++++++++++++++++++++++-------------------------- 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index a7a19190..24adf5e1 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -52,6 +52,14 @@ #include #include +#define OCAPIDBG(dev, fmt, a...) prlog(PR_DEBUG, "OCAPI[%d:%d]: " fmt, \ + dev->npu->chip_id, dev->index, ## a) +#define OCAPIINF(dev, fmt, a...) prlog(PR_INFO, "OCAPI[%d:%d]: " fmt, \ + dev->npu->chip_id, dev->index, ## a) +#define OCAPIERR(dev, fmt, a...) prlog(PR_ERR, "OCAPI[%d:%d]: " fmt, \ + dev->npu->chip_id, dev->index, ## a) + + #define NPU_IRQ_LEVELS 35 #define NPU_IRQ_LEVELS_XSL 23 #define MAX_PE_HANDLE ((1 << 15) - 1) @@ -787,15 +795,16 @@ static void setup_afu_config_bars(uint32_t gcid, uint32_t scom_base, dev->bars[1].npu2_bar.size = size; } -static void otl_enabletx(uint32_t gcid, uint32_t scom_base, uint64_t index) +static void otl_enabletx(uint32_t gcid, uint32_t scom_base, + struct npu2_dev *dev) { - uint64_t stack = index_to_stack(index); - uint64_t block = index_to_block(index); + uint64_t stack = index_to_stack(dev->index); + uint64_t block = index_to_block(dev->index); uint64_t reg; /* OTL Config 2 Register */ /* Transmit Enable */ - prlog(PR_DEBUG, "OCAPI: %s: Enabling TX\n", __func__); + OCAPIDBG(dev, "Enabling TX\n"); reg = 0; reg |= NPU2_OTL_CONFIG2_TX_SEND_EN; npu2_scom_write(gcid, scom_base, NPU2_OTL_CONFIG2(stack, block), @@ -803,7 +812,7 @@ static void otl_enabletx(uint32_t gcid, uint32_t scom_base, uint64_t index) reg = npu2_scom_read(gcid, scom_base, NPU2_OTL_VC_CREDITS(stack, block), NPU2_MISC_DA_LEN_8B); - prlog(PR_DEBUG, "OCAPI: credit counter: %llx\n", reg); + OCAPIDBG(dev, "credit counter: %llx\n", reg); /* TODO: Abort if credits are zero */ } @@ -855,7 +864,7 @@ err: * @fwts-advice There was an error attempting to send * a reset signal over I2C to the OpenCAPI device. */ - prlog(PR_ERR, "OCAPI: Error writing I2C reset signal: %d\n", rc); + OCAPIERR(dev, "Error writing I2C reset signal: %d\n", rc); } static void deassert_reset(struct npu2_dev *dev) @@ -874,7 +883,7 @@ static void deassert_reset(struct npu2_dev *dev) * @fwts-advice There was an error attempting to send * a reset signal over I2C to the OpenCAPI device. */ - prlog(PR_ERR, "OCAPI: Error writing I2C reset signal: %d\n", rc); + OCAPIERR(dev, "Error writing I2C reset signal: %d\n", rc); } } @@ -894,12 +903,11 @@ static bool i2c_presence_detect(struct npu2_dev *dev) SMBUS_READ, 0, 1, &state, 1, 120); if (rc) { - prlog(PR_ERR, "OCAPI: error detecting link presence: %d\n", - rc); + OCAPIERR(dev, "error detecting link presence: %d\n", rc); return true; /* assume link exists */ } - prlog(PR_DEBUG, "OCAPI: I2C presence detect: 0x%x\n", state); + OCAPIDBG(dev, "I2C presence detect: 0x%x\n", state); switch (dev->index) { case 2: @@ -909,7 +917,7 @@ static bool i2c_presence_detect(struct npu2_dev *dev) data = platform.ocapi->i2c_presence_odl1; break; default: - prlog(PR_ERR, "OCAPI: presence detection on invalid link\n"); + OCAPIERR(dev, "presence detection on invalid link\n"); return true; } /* Presence detect bits are active low */ @@ -1053,17 +1061,13 @@ static int64_t npu2_opencapi_retry_state(struct pci_slot *slot) * This indicates a hardware or firmware bug. OpenCAPI * functionality will not be available on this link. */ - prlog(PR_ERR, - "OCAPI: Link %d on chip %u failed to train\n", - dev->index, chip_id); - prlog(PR_ERR, "OCAPI: Final link status: %016llx\n", + OCAPIERR(dev, + "Link failed to train, final link status: %016llx\n", get_odl_status(chip_id, dev->index)); return OPAL_HARDWARE; } - prlog(PR_ERR, - "OCAPI: Link %d on chip %u failed to train, retrying\n", - dev->index, chip_id); + OCAPIERR(dev, "Link failed to train, retrying\n"); pci_slot_set_state(slot, OCAPI_SLOT_FRESET_INIT); return pci_slot_set_sm_timeout(slot, msecs_to_tb(1)); } @@ -1077,15 +1081,13 @@ static int64_t npu2_opencapi_poll_link(struct pci_slot *slot) switch (slot->state) { case OCAPI_SLOT_NORMAL: case OCAPI_SLOT_LINK_START: - prlog(PR_DEBUG, "OCAPI: LINK: Start polling\n"); + OCAPIDBG(dev, "Start polling\n"); pci_slot_set_state(slot, OCAPI_SLOT_LINK_WAIT); /* fall-through */ case OCAPI_SLOT_LINK_WAIT: reg = get_odl_status(chip_id, dev->index); if (GETFIELD(OB_ODL_STATUS_TRAINING_STATE_MACHINE, reg) == 0x7) { - prlog(PR_NOTICE, - "OCAPI: Link %d on chip %u trained in %lld ms\n", - dev->index, chip_id, + OCAPIINF(dev, "link trained in %lld ms\n", OCAPI_LINK_TRAINING_TIMEOUT - slot->retries); pci_slot_set_state(slot, OCAPI_SLOT_LINK_TRAINED); return pci_slot_set_sm_timeout(slot, msecs_to_tb(1)); @@ -1096,13 +1098,12 @@ static int64_t npu2_opencapi_poll_link(struct pci_slot *slot) return pci_slot_set_sm_timeout(slot, msecs_to_tb(1)); case OCAPI_SLOT_LINK_TRAINED: - otl_enabletx(chip_id, dev->npu->xscom_base, dev->index); + otl_enabletx(chip_id, dev->npu->xscom_base, dev); pci_slot_set_state(slot, OCAPI_SLOT_NORMAL); return OPAL_SUCCESS; default: - prlog(PR_ERR, "OCAPI: LINK: unexpected slot state %08x\n", - slot->state); + OCAPIERR(dev, "unexpected slot state %08x\n", slot->state); } pci_slot_set_state(slot, OCAPI_SLOT_NORMAL); @@ -1111,7 +1112,9 @@ static int64_t npu2_opencapi_poll_link(struct pci_slot *slot) static int64_t npu2_opencapi_creset(struct pci_slot *slot __unused) { - prlog(PR_ERR, "OCAPI: creset not supported\n"); + struct npu2_dev *dev = phb_to_npu2_dev_ocapi(slot->phb); + + OCAPIERR(dev, "creset not supported\n"); return OPAL_UNSUPPORTED; } @@ -1124,7 +1127,7 @@ static int64_t npu2_opencapi_freset(struct pci_slot *slot) switch (slot->state) { case OCAPI_SLOT_NORMAL: case OCAPI_SLOT_FRESET_START: - prlog(PR_DEBUG, "OCAPI: FRESET: Starts\n"); + OCAPIDBG(dev, "FRESET starts\n"); if (slot->ops.get_presence_state) slot->ops.get_presence_state(slot, &presence); @@ -1134,9 +1137,7 @@ static int64_t npu2_opencapi_freset(struct pci_slot *slot) * should consider powering off the unused * lanes to save energy */ - prlog(PR_INFO, - "OCAPI: no card detected on link %d, chip %d\n", - dev->index, chip_id); + OCAPIINF(dev, "no card detected\n"); return OPAL_SUCCESS; } slot->link_retries = OCAPI_LINK_TRAINING_RETRIES; @@ -1172,7 +1173,7 @@ static int64_t npu2_opencapi_freset(struct pci_slot *slot) return slot->ops.poll_link(slot); default: - prlog(PR_ERR, "OCAPI: FRESET: unexpected slot state %08x\n", + OCAPIERR(dev, "FRESET: unexpected slot state %08x\n", slot->state); } pci_slot_set_state(slot, OCAPI_SLOT_NORMAL); @@ -1181,7 +1182,9 @@ static int64_t npu2_opencapi_freset(struct pci_slot *slot) static int64_t npu2_opencapi_hreset(struct pci_slot *slot __unused) { - prlog(PR_ERR, "OCAPI: hreset not supported\n"); + struct npu2_dev *dev = phb_to_npu2_dev_ocapi(slot->phb); + + OCAPIERR(dev, "hreset not supported\n"); return OPAL_UNSUPPORTED; } @@ -1532,12 +1535,12 @@ static void setup_debug_training_state(struct npu2_dev *dev) switch (npu2_ocapi_training_state) { case NPU2_TRAIN_PRBS31: - prlog(PR_INFO, "OCAPI: sending PRBS31 pattern per NVRAM setting\n"); + OCAPIINF(dev, "sending PRBS31 pattern per NVRAM setting\n"); npu2_opencapi_phy_prbs31(dev); break; case NPU2_TRAIN_NONE: - prlog(PR_INFO, "OCAPI: link not trained per NVRAM setting\n"); + OCAPIINF(dev, "link not trained per NVRAM setting\n"); break; default: assert(false); @@ -1942,7 +1945,7 @@ static bool is_template_supported(unsigned int templ, long capabilities) return !!(capabilities & (1ull << templ)); } -static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, +static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t __unused bdfn, long capabilities, uint64_t rate_phys, int rate_sz) { struct phb *phb = pci_get_phb(phb_id); @@ -1995,8 +1998,7 @@ static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, npu2_scom_write(dev->npu->chip_id, dev->npu->xscom_base, NPU2_OTL_CONFIG1(stack, block), NPU2_MISC_DA_LEN_8B, reg); - prlog(PR_DEBUG, "OCAPI: Link %llx:%x, TL conf1 register set to %llx\n", - phb_id, bdfn, reg); + OCAPIDBG(dev, "OTL configuration 1 register set to %llx\n", reg); return OPAL_SUCCESS; } opal_call(OPAL_NPU_TL_SET, opal_npu_tl_set, 5);