From patchwork Wed Apr 11 21:16:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 897409 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-91503-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="Pf857PKZ"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40Lxg908rqz9s25 for ; Thu, 12 Apr 2018 07:16:36 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id; q=dns; s= default; b=DgeY6+3YJLurYXBAOpdrmoZ4FzIypWYE3m0FRvdCWHhFjBv86kiOj j6tDqoLqX4SWGZWUSQDbd7SfQCr59oxGFB+Fz9Q9DNgrlwEykEvLIdMdEujBRJ2d ueB+2PgRQlDk8uZAtM1Qoc77UcwvJ6dOPWlbx7106J2F0Bh9jy5XM0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id; s=default; bh=aiJeB/048WUdfWF7LfrPWN4Ypmg=; b=Pf857PKZrZJnrDhQSjG0sElkK8Ra /bhYlhD4Np1VgNPn7JBjpGgnatgcFudZjC4SVViHokt6Yl0QtQoEQI0nVbL90iA+ i9josQc6tg/wrvOwiSMTM6e2ZUXaA4lh3rXtLpcqZltzAweMDLcOhHHIBNmIYh9b GemPvideqcY0AEE= Received: (qmail 117516 invoked by alias); 11 Apr 2018 21:16:30 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 117501 invoked by uid 89); 11 Apr 2018 21:16:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-qt0-f177.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=/58BtFjtASY33cpSfVmiwgP6rfD1BfvlfF+4gZiXpwM=; b=Kyer78jRfTC/PMXgYiIorVaDaKkyGvk2Nuc6XD+gBwRlWUprvU//OBJxBJLyR7o3sq jRf1W11VdD5IQB1NNBT2unvd1UVR+KVjstbfP9BlYsIi2EMytdruaOv3gUw8ZBJdPOY9 FYjtJxGM+Ga8utoZXPeinVbafqOdYEkuC2BgPnrEja/wb4JCucJlih20hWKXexv+UXIQ VmVxeYRmROmwkkQA8dqCr4UeLe1coTmwecqlofllsTTIWv2RXMZ7gItwKzNio+Vl1rOe Yj4lKNAFW4vF+COXdfamuI4FeUfZsQS1XyNr1p/tCxFTMayOvCYXNXq3hhyERhRVSYFU zcKA== X-Gm-Message-State: ALQs6tAUk1n6nLzo1NvisrNeiAngpvBh7V6kFlm5Owpj1Y86CmqB7ykk fC5t+QBrvMctPyI3wLVg7+41+vHVl5s= X-Google-Smtp-Source: AIpwx48bLFiYRmzmhK94ci3QeF7BJkCXOmUPQ2VCfAh3ut6G7pOoHqsfwxwT7BZlQ6wpuCrB0iXlTw== X-Received: by 10.200.4.9 with SMTP id v9mr9642389qtg.69.1523481385978; Wed, 11 Apr 2018 14:16:25 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 1/4] arm: Fix armv7 neon memchr on ARM mode Date: Wed, 11 Apr 2018 18:16:15 -0300 Message-Id: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> Current optimized armv7 neon memchr uses the NO_THUMB wrongly to conditionalize thumb instruction usage. The flags is meant to be defined before sysdep.h inclusion and to indicate the assembly requires to build in ARM mode, not to check whether thumb is enable or not. This patch fixes it by using the GCC provided '__thumb__' instead. Also, even if the implementation is fixed to not use thumb instructions it was clearly not proper checked in ARM mode: the carry bit flag will be reset in previous 'cmp synd, #0' and thus the 'bhi cntin, #0' won't be able to branch correctly if the loop finishes with 'cntin' being negative (indicating that some bytes still require to be checked). This patch also fixes it by checking the carry flag in previous loop iteration directly (in ARM mode it will run both '.Lmasklast' and '.Ltail' even if no byte is found in last loop iteration). Checked on arm-linux-gnueabihf (with -marm and -mthumb mode). [BZ #23031] * sysdeps/arm/armv7/multiarch/memchr_neon.S (memchr): Fix tail check on ARM mode. (NO_THUMB): Check __thumb__ instead. --- ChangeLog | 7 +++++++ sysdeps/arm/armv7/multiarch/memchr_neon.S | 9 +++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/sysdeps/arm/armv7/multiarch/memchr_neon.S b/sysdeps/arm/armv7/multiarch/memchr_neon.S index 1b2ae75..1b2a69d 100644 --- a/sysdeps/arm/armv7/multiarch/memchr_neon.S +++ b/sysdeps/arm/armv7/multiarch/memchr_neon.S @@ -68,7 +68,7 @@ * allows to identify exactly which byte has matched. */ -#ifndef NO_THUMB +#ifdef __thumb__ .thumb_func #else .arm @@ -132,7 +132,7 @@ ENTRY(memchr) /* The first block can also be the last */ bls .Lmasklast /* Have we found something already? */ -#ifndef NO_THUMB +#ifdef __thumb__ cbnz synd, .Ltail #else cmp synd, #0 @@ -176,14 +176,11 @@ ENTRY(memchr) vpadd.i8 vdata0_0, vdata0_0, vdata1_0 vpadd.i8 vdata0_0, vdata0_0, vdata0_0 vmov synd, vdata0_0[0] -#ifndef NO_THUMB +#ifdef __thumb__ cbz synd, .Lnotfound bhi .Ltail /* Uses the condition code from subs cntin, cntin, #32 above. */ #else - cmp synd, #0 - beq .Lnotfound - cmp cntin, #0 bhi .Ltail #endif