| Message ID | 20180410183212.16787-6-jae.hyun.yoo@linux.intel.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | PECI device driver introduction | expand |
On 11 April 2018 at 04:02, Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> wrote: > This commit adds PECI bus/adapter node of AST24xx/AST25xx into > aspeed-g4 and aspeed-g5. > The patches to the device trees get merged by the ASPEED maintainer (me). Once you have the bindings reviewed you can send the patches to me and the linux-aspeed list (I've got a pending patch to maintainers that will ensure get_maintainers.pl does the right thing as far as email addresses go). I'd suggest dropping it from your series and re-sending once the bindings and driver are reviewed. Cheers, Joel
On 4/11/2018 4:52 AM, Joel Stanley wrote: > On 11 April 2018 at 04:02, Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> wrote: >> This commit adds PECI bus/adapter node of AST24xx/AST25xx into >> aspeed-g4 and aspeed-g5. >> > > The patches to the device trees get merged by the ASPEED maintainer > (me). Once you have the bindings reviewed you can send the patches to > me and the linux-aspeed list (I've got a pending patch to maintainers > that will ensure get_maintainers.pl does the right thing as far as > email addresses go). > > I'd suggest dropping it from your series and re-sending once the > bindings and driver are reviewed. > > Cheers, > > Joel > Do you mean that bindings and driver of ASPEED peci adapter driver including documents? Thanks, -Jae
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 518d2bc7c7fc..f7992eee4d1f 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -29,6 +29,7 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &vuart; + peci0 = &peci0; }; cpus { @@ -270,6 +271,13 @@ }; }; + peci: peci@1e78b000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e78b000 0x60>; + }; + uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>; @@ -313,6 +321,23 @@ }; }; +&peci { + peci0: peci-bus@0 { + compatible = "aspeed,ast2400-peci"; + reg = <0x0 0x60>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + clock-frequency = <24000000>; + msg-timing-nego = <1>; + addr-timing-nego = <1>; + rd-sampling-point = <8>; + cmd-timeout-ms = <1000>; + status = "disabled"; + }; +}; + &i2c { i2c_ic: interrupt-controller@0 { #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index f9917717dd08..278791dba8a0 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -29,6 +29,7 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &vuart; + peci0 = &peci0; }; cpus { @@ -320,6 +321,13 @@ }; }; + peci: peci@1e78b000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e78b000 0x60>; + }; + uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>; @@ -363,6 +371,23 @@ }; }; +&peci { + peci0: peci-bus@0 { + compatible = "aspeed,ast2500-peci"; + reg = <0x0 0x60>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + clock-frequency = <24000000>; + msg-timing-nego = <1>; + addr-timing-nego = <1>; + rd-sampling-point = <8>; + cmd-timeout-ms = <1000>; + status = "disabled"; + }; +}; + &i2c { i2c_ic: interrupt-controller@0 { #interrupt-cells = <1>;