[v3,2/4] gpio: pca953x: add register definitions for pcal6524 and fix address calculation

Message ID 0e9bea79eae7504e61fabdb4a0311f8fdc2f6b25.1523376423.git.hns@goldelico.com
State New
Headers show
Series
  • pcal6524 extensions and fixes for pca953x driver
Related show

Commit Message

H. Nikolaus Schaller April 10, 2018, 4:07 p.m.
PCAL chips ("L" seems to stand for "latched") have additional
registers starting at address 0x40 to control the latches,
interrupt mask, pull-up and pull down etc.

The constants are so far defined in a way that they fit for
the pcal9555a when shifted by the number of banks, i.e. multiplied
by 2.

Now the pcal6524 has 3 banks which means the relative offset
must be multiplied by 4 which gives a wrong result if not done
carefully, since the base offset is already included in the offset.

For the basic registers shared with all pca93xx/tca64xx chips
there is no such offset.

Therefore, we add code to adjust the register number for exended
registers to the 24 bit accessor functions.

And we add additional register offset constants (not yet used by
the driver code) which are specific to the pcal6524.

Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 drivers/gpio/gpio-pca953x.c | 50 ++++++++++++++++++++++++++++++---------------
 1 file changed, 34 insertions(+), 16 deletions(-)

Comments

Andy Shevchenko April 10, 2018, 6:06 p.m. | #1
On Tue, Apr 10, 2018 at 7:07 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
> PCAL chips ("L" seems to stand for "latched") have additional
> registers starting at address 0x40 to control the latches,
> interrupt mask, pull-up and pull down etc.
>
> The constants are so far defined in a way that they fit for
> the pcal9555a when shifted by the number of banks, i.e. multiplied
> by 2.
>
> Now the pcal6524 has 3 banks which means the relative offset
> must be multiplied by 4 which gives a wrong result if not done
> carefully, since the base offset is already included in the offset.
>
> For the basic registers shared with all pca93xx/tca64xx chips
> there is no such offset.
>
> Therefore, we add code to adjust the register number for exended
> registers to the 24 bit accessor functions.
>
> And we add additional register offset constants (not yet used by
> the driver code) which are specific to the pcal6524.
>

First of all, as I said, please split this to two patches. Don't mix the things.


> +       /* adjust register address for pcal6524 */
> +       if (reg >= PCAL953X_OUT_STRENGTH)
> +               reg -= PCAL953X_OUT_STRENGTH >> 1;
> +

Give me some days to think about it.
H. Nikolaus Schaller April 11, 2018, 5 a.m. | #2
Hi Andy,

> Am 10.04.2018 um 20:06 schrieb Andy Shevchenko <andy.shevchenko@gmail.com>:
> 
> On Tue, Apr 10, 2018 at 7:07 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
>> PCAL chips ("L" seems to stand for "latched") have additional
>> registers starting at address 0x40 to control the latches,
>> interrupt mask, pull-up and pull down etc.
>> 
>> The constants are so far defined in a way that they fit for
>> the pcal9555a when shifted by the number of banks, i.e. multiplied
>> by 2.
>> 
>> Now the pcal6524 has 3 banks which means the relative offset
>> must be multiplied by 4 which gives a wrong result if not done
>> carefully, since the base offset is already included in the offset.
>> 
>> For the basic registers shared with all pca93xx/tca64xx chips
>> there is no such offset.
>> 
>> Therefore, we add code to adjust the register number for exended
>> registers to the 24 bit accessor functions.
>> 
>> And we add additional register offset constants (not yet used by
>> the driver code) which are specific to the pcal6524.
>> 
> 
> First of all, as I said, please split this to two patches. Don't mix the things.

Ok. Queued for v4.

> 
> 
>> +       /* adjust register address for pcal6524 */
>> +       if (reg >= PCAL953X_OUT_STRENGTH)
>> +               reg -= PCAL953X_OUT_STRENGTH >> 1;
>> +
> 
> Give me some days to think about it.

No problem. I'll wait with v4.

The only alternative I would see is to add new accessor function
pointers for the extended registers and have 0x00 based offsets,
but that is IMHO more ugly.

BR and thanks,
Nikolaus

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H. Nikolaus Schaller April 25, 2018, 6:05 p.m. | #3
Hi Andy,

> Am 11.04.2018 um 07:00 schrieb H. Nikolaus Schaller <hns@goldelico.com>:
> 
> Hi Andy,
> 
>> Am 10.04.2018 um 20:06 schrieb Andy Shevchenko <andy.shevchenko@gmail.com>:
>> 
>> On Tue, Apr 10, 2018 at 7:07 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
>>> PCAL chips ("L" seems to stand for "latched") have additional
>>> registers starting at address 0x40 to control the latches,
>>> interrupt mask, pull-up and pull down etc.
>>> 
>>> The constants are so far defined in a way that they fit for
>>> the pcal9555a when shifted by the number of banks, i.e. multiplied
>>> by 2.
>>> 
>>> Now the pcal6524 has 3 banks which means the relative offset
>>> must be multiplied by 4 which gives a wrong result if not done
>>> carefully, since the base offset is already included in the offset.
>>> 
>>> For the basic registers shared with all pca93xx/tca64xx chips
>>> there is no such offset.
>>> 
>>> Therefore, we add code to adjust the register number for exended
>>> registers to the 24 bit accessor functions.
>>> 
>>> And we add additional register offset constants (not yet used by
>>> the driver code) which are specific to the pcal6524.
>>> 
>> 
>> First of all, as I said, please split this to two patches. Don't mix the things.
> 
> Ok. Queued for v4.
> 
>> 
>> 
>>> +       /* adjust register address for pcal6524 */
>>> +       if (reg >= PCAL953X_OUT_STRENGTH)
>>> +               reg -= PCAL953X_OUT_STRENGTH >> 1;
>>> +
>> 
>> Give me some days to think about it.

Any news on this?

I am waiting for your advice before submitting v4 (with pending updates for the other patches).

> No problem. I'll wait with v4.
> 
> The only alternative I would see is to add new accessor function
> pointers for the extended registers and have 0x00 based offsets,
> but that is IMHO more ugly.
> 
> BR and thanks,
> Nikolaus

BR and thanks,
Nikolaus


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Andy Shevchenko April 26, 2018, 10:06 a.m. | #4
On Wed, Apr 25, 2018 at 9:05 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
>> Am 11.04.2018 um 07:00 schrieb H. Nikolaus Schaller <hns@goldelico.com>:
>>> Am 10.04.2018 um 20:06 schrieb Andy Shevchenko <andy.shevchenko@gmail.com>:
>>> On Tue, Apr 10, 2018 at 7:07 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:

>>>> PCAL chips ("L" seems to stand for "latched") have additional
>>>> registers starting at address 0x40 to control the latches,
>>>> interrupt mask, pull-up and pull down etc.
>>>>
>>>> The constants are so far defined in a way that they fit for
>>>> the pcal9555a when shifted by the number of banks, i.e. multiplied
>>>> by 2.
>>>>
>>>> Now the pcal6524 has 3 banks which means the relative offset
>>>> must be multiplied by 4 which gives a wrong result if not done
>>>> carefully, since the base offset is already included in the offset.
>>>>
>>>> For the basic registers shared with all pca93xx/tca64xx chips
>>>> there is no such offset.
>>>>
>>>> Therefore, we add code to adjust the register number for exended
>>>> registers to the 24 bit accessor functions.
>>>>
>>>> And we add additional register offset constants (not yet used by
>>>> the driver code) which are specific to the pcal6524.

>>> First of all, as I said, please split this to two patches. Don't mix the things.
>> Ok. Queued for v4.

I actually think it would be even more patches:
 - move to hex from dec
 - add new definitions for PCAL953x
 - append new code for registers (see below)
 - add definitions for PCAL6524

>>>> +       /* adjust register address for pcal6524 */
>>>> +       if (reg >= PCAL953X_OUT_STRENGTH)
>>>> +               reg -= PCAL953X_OUT_STRENGTH >> 1;
>>>> +
>>>
>>> Give me some days to think about it.

So, what about something like:

--- 8< --- 8< ---
#define PCAL953X_GPIO_MASK GENMASK(5,0) // this makes sense even for
your initial solution

int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
int addr = (reg & PCAL953X_GPIO_MASK) << bank_shift;
int pinctrl = (reg & ~PCAL953X_GPIO_MASK) << 1;

return i2c_smbus_write_i2c_block_data(chip->client,
                                             pinctrl | addr  | REG_ADDR_AI,
                                             NBANK(chip), val);

// similar for read.

--- 8< --- 8< ---

Keep in mind your solution has a bug for registers starting from 0x30.
H. Nikolaus Schaller April 26, 2018, 10:17 a.m. | #5
Hi Andy,

> Am 26.04.2018 um 12:06 schrieb Andy Shevchenko <andy.shevchenko@gmail.com>:
> 
> On Wed, Apr 25, 2018 at 9:05 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
>>> Am 11.04.2018 um 07:00 schrieb H. Nikolaus Schaller <hns@goldelico.com>:
>>>> Am 10.04.2018 um 20:06 schrieb Andy Shevchenko <andy.shevchenko@gmail.com>:
>>>> On Tue, Apr 10, 2018 at 7:07 PM, H. Nikolaus Schaller <hns@goldelico.com> wrote:
> 
>>>>> PCAL chips ("L" seems to stand for "latched") have additional
>>>>> registers starting at address 0x40 to control the latches,
>>>>> interrupt mask, pull-up and pull down etc.
>>>>> 
>>>>> The constants are so far defined in a way that they fit for
>>>>> the pcal9555a when shifted by the number of banks, i.e. multiplied
>>>>> by 2.
>>>>> 
>>>>> Now the pcal6524 has 3 banks which means the relative offset
>>>>> must be multiplied by 4 which gives a wrong result if not done
>>>>> carefully, since the base offset is already included in the offset.
>>>>> 
>>>>> For the basic registers shared with all pca93xx/tca64xx chips
>>>>> there is no such offset.
>>>>> 
>>>>> Therefore, we add code to adjust the register number for exended
>>>>> registers to the 24 bit accessor functions.
>>>>> 
>>>>> And we add additional register offset constants (not yet used by
>>>>> the driver code) which are specific to the pcal6524.
> 
>>>> First of all, as I said, please split this to two patches. Don't mix the things.
>>> Ok. Queued for v4.
> 
> I actually think it would be even more patches:
> - move to hex from dec
> - add new definitions for PCAL953x
> - append new code for registers (see below)
> - add definitions for PCAL6524

It is already done in my local git,
just waiting for the address thing...

> 
>>>>> +       /* adjust register address for pcal6524 */
>>>>> +       if (reg >= PCAL953X_OUT_STRENGTH)
>>>>> +               reg -= PCAL953X_OUT_STRENGTH >> 1;
>>>>> +
>>>> 
>>>> Give me some days to think about it.
> 
> So, what about something like:
> 
> --- 8< --- 8< ---
> #define PCAL953X_GPIO_MASK GENMASK(5,0) // this makes sense even for
> your initial solution
> 
> int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
> int addr = (reg & PCAL953X_GPIO_MASK) << bank_shift;
> int pinctrl = (reg & ~PCAL953X_GPIO_MASK) << 1;

Ok! Intersting idea.

Basically decomposes register bank number (pinctrl) and register offset (addr)
and shifts them differently.

> 
> return i2c_smbus_write_i2c_block_data(chip->client,
>                                             pinctrl | addr  | REG_ADDR_AI,
>                                             NBANK(chip), val);
> 
> // similar for read.

Looks good. I'll test asap.

BR and thanks,
Nikolaus

> 
> --- 8< --- 8< ---
> 
> Keep in mind your solution has a bug for registers starting from 0x30.
> 
> -- 
> With Best Regards,
> Andy Shevchenko

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Patch

diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 4a075619b93e..022307d328ff 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -25,25 +25,35 @@ 
 
 #include <asm/unaligned.h>
 
-#define PCA953X_INPUT		0
-#define PCA953X_OUTPUT		1
-#define PCA953X_INVERT		2
-#define PCA953X_DIRECTION	3
+#define PCA953X_INPUT		0x0
+#define PCA953X_OUTPUT		0x1
+#define PCA953X_INVERT		0x2
+#define PCA953X_DIRECTION	0x3
 
 #define REG_ADDR_AI		0x80
 
-#define PCA957X_IN		0
-#define PCA957X_INVRT		1
-#define PCA957X_BKEN		2
-#define PCA957X_PUPD		3
-#define PCA957X_CFG		4
-#define PCA957X_OUT		5
-#define PCA957X_MSK		6
-#define PCA957X_INTS		7
-
-#define PCAL953X_IN_LATCH	34
-#define PCAL953X_INT_MASK	37
-#define PCAL953X_INT_STAT	38
+#define PCA957X_IN		0x00
+#define PCA957X_INVRT		0x01
+#define PCA957X_BKEN		0x02
+#define PCA957X_PUPD		0x03
+#define PCA957X_CFG		0x04
+#define PCA957X_OUT		0x05
+#define PCA957X_MSK		0x06
+#define PCA957X_INTS		0x07
+
+#define PCAL953X_OUT_STRENGTH	0x20
+#define PCAL953X_IN_LATCH	0x22
+#define PCAL953X_PULL_EN	0x23
+#define PCAL953X_PULL_SEL	0x24
+#define PCAL953X_INT_MASK	0x25
+#define PCAL953X_INT_STAT	0x26
+#define PCAL953X_OUT_CONF	0x27
+
+#define PCAL6524_INT_EDGE	0x28
+#define PCAL6524_INT_CLR	0x2a
+#define PCAL6524_IN_STATUS	0x2b
+#define PCAL6524_OUT_INDCONF	0x2c
+#define PCAL6524_DEBOUNCE	0x2d
 
 #define PCA_GPIO_MASK		0x00FF
 #define PCA_INT			0x0100
@@ -208,6 +218,10 @@  static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
 {
 	int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
 
+	/* adjust register address for pcal6524 */
+	if (reg >= PCAL953X_OUT_STRENGTH)
+		reg -= PCAL953X_OUT_STRENGTH >> 1;
+
 	return i2c_smbus_write_i2c_block_data(chip->client,
 					      (reg << bank_shift) | REG_ADDR_AI,
 					      NBANK(chip), val);
@@ -250,6 +264,10 @@  static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
 {
 	int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
 
+	/* adjust register address for pcal6524 */
+	if (reg >= PCAL953X_OUT_STRENGTH)
+		reg -= PCAL953X_OUT_STRENGTH >> 1;
+
 	return i2c_smbus_read_i2c_block_data(chip->client,
 					     (reg << bank_shift) | REG_ADDR_AI,
 					     NBANK(chip), val);