[v3,07/10] PCI: dwc: Define maximum number of vectors

Message ID 04c2a7739be0a211e2123c54bf55368624a3ecd1.1523360166.git.gustavo.pimentel@synopsys.com
State Superseded
Delegated to: Lorenzo Pieralisi
Headers show
  • Designware EP support and code clean up
Related show

Commit Message

Gustavo Pimentel April 10, 2018, 12:58 p.m.
Adds a callback that defines the maximum number of vectors that can be use
by the Root Complex.

Since this is a parameter associated to each SoC IP setting, makes sense to
be configurable and easily visible to future modifications.

The designware IP supports a maximum of 256 vectors.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.

 drivers/pci/dwc/pcie-designware-plat.c | 6 ++++++
 1 file changed, 6 insertions(+)


diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c
index 4be9c3a..04afa80 100644
--- a/drivers/pci/dwc/pcie-designware-plat.c
+++ b/drivers/pci/dwc/pcie-designware-plat.c
@@ -48,8 +48,14 @@  static int dw_plat_pcie_host_init(struct pcie_port *pp)
 	return 0;
+static void dw_plat_set_num_vectors(struct pcie_port *pp)
+	pp->num_vectors = MAX_MSI_IRQS;
 static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
 	.host_init = dw_plat_pcie_host_init,
+	.set_num_vectors = dw_plat_set_num_vectors,
 static int dw_plat_pcie_establish_link(struct dw_pcie *pci)