From patchwork Wed Apr 4 17:22:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 895082 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="QhU9ay69"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40GXt96PvVz9s1l for ; Thu, 5 Apr 2018 03:25:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751740AbeDDRZL (ORCPT ); Wed, 4 Apr 2018 13:25:11 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:39459 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751368AbeDDRZJ (ORCPT ); Wed, 4 Apr 2018 13:25:09 -0400 Received: by mail-pl0-f66.google.com with SMTP id s24-v6so14985490plq.6 for ; Wed, 04 Apr 2018 10:25:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=79fkHFqwafWO4Y9s6ATm0Hzlv8D96ZrA+UGwyt1AFXU=; b=QhU9ay691jOSRUiZb+lS1n+FUTK+EqEsOYGja3mDJLlKfvXNXLpqWLCWVKxUHoXaI/ ZygTGgC/Z/SWnrPdGFDyDj5mqMoctN6VXnNQbEoHmBIC3+46G5LWGAb1zjGpPvmN/B1w 3Jt2w+tt7tEHUei+3WdYkxkvE6bAxPw33SFkY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=79fkHFqwafWO4Y9s6ATm0Hzlv8D96ZrA+UGwyt1AFXU=; b=qRJjTviozg4XKtsghymsoJKZ5zfPN1vuwDDul4XkHvS3sZKgQFL2z9cTm6O5pLazEv MM9BJyxkuteUbeKlIis1FdLTmDYUEDlg+pyYah+gV0Op1pIsJDY8D/xl21NDDTatAaVS 6A0v6yKwULDAUeqQNq5OwqvLOBRfv0WYeDks6fJHquCWQBbX2cu1E+bFfCk/s7zOIL9w Ak4hmVtAAi4gHCdYaHdQANDie3sdfbfITWzG/iKYzNCAovkw7nTPM5a1do8lTn1XVj6J VvtHwCXHZyfWQZWku+nmM7Wb7FKUJdtRbSbMtepKb26cfj6fNL1D1XEn2BrfaVo+N7ny Abkg== X-Gm-Message-State: AElRT7EfSMHE2JS3S01uzvYlUAtT/2Ns8P8HlRGPfyNyF3sa3P1tQrB/ er0x5qwFGK3tWTA8Hy0efv2g X-Google-Smtp-Source: AIpwx48Foh6owUF6SkElji9ucUmowU9cJNo1UUigFd6lBhr3I6j3feGN5jrrrvVPtbYxwkEb/A4zJQ== X-Received: by 2002:a17:902:9308:: with SMTP id bc8-v6mr19429209plb.189.1522862708465; Wed, 04 Apr 2018 10:25:08 -0700 (PDT) Received: from localhost.localdomain ([2405:204:730d:2b78:a8cb:9f26:6eed:eba5]) by smtp.gmail.com with ESMTPSA id t5sm10791384pgr.69.2018.04.04.10.25.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Apr 2018 10:25:07 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v7 7/9] gpio: Add gpio driver for Actions OWL S900 SoC Date: Wed, 4 Apr 2018 22:52:56 +0530 Message-Id: <20180404172258.7678-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180404172258.7678-1-manivannan.sadhasivam@linaro.org> References: <20180404172258.7678-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add gpio driver for Actions Semi OWL family S900 SoC. Set of registers controlling the gpio shares the same register range with pinctrl block. GPIO registers are organized as 6 banks and each bank controls the maximum of 32 gpios. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andy Shevchenko --- drivers/gpio/Kconfig | 8 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-owl.c | 184 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 193 insertions(+) create mode 100644 drivers/gpio/gpio-owl.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8dbb2280538d..75533f55ad0e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -364,6 +364,14 @@ config GPIO_OMAP help Say yes here to enable GPIO support for TI OMAP SoCs. +config GPIO_OWL + tristate "Actions Semi OWL GPIO support" + default ARCH_ACTIONS + depends on ARCH_ACTIONS || COMPILE_TEST + depends on OF_GPIO + help + Say yes here to enable GPIO support for Actions Semi OWL SoCs. + config GPIO_PL061 bool "PrimeCell PL061 GPIO support" depends on ARM_AMBA diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index cccb0d40846c..b2bb11d4675f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -91,6 +91,7 @@ obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o obj-$(CONFIG_GPIO_OMAP) += gpio-omap.o +obj-$(CONFIG_GPIO_OWL) += gpio-owl.o obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o obj-$(CONFIG_GPIO_PCH) += gpio-pch.o diff --git a/drivers/gpio/gpio-owl.c b/drivers/gpio/gpio-owl.c new file mode 100644 index 000000000000..354636229fee --- /dev/null +++ b/drivers/gpio/gpio-owl.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OWL SoC's GPIO driver + * + * Copyright (c) 2018 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_OUTEN 0x0000 +#define GPIO_INEN 0x0004 +#define GPIO_DAT 0x0008 + +struct owl_gpio { + struct gpio_chip gpio; + void __iomem *base; + spinlock_t lock; +}; + +static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag) +{ + u32 val; + + val = readl_relaxed(base); + + if (flag) + val |= BIT(pin); + else + val &= ~BIT(pin); + + writel_relaxed(val, base); +} + +static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + + /* + * GPIOs have higher priority over other modules, so either setting + * them as OUT or IN is sufficient + */ + spin_lock(&gpio->lock); + owl_gpio_update_reg(gpio->base + GPIO_OUTEN, offset, true); + spin_unlock(&gpio->lock); + + return 0; +} + +static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + + spin_lock(&gpio->lock); + /* disable gpio output */ + owl_gpio_update_reg(gpio->base + GPIO_OUTEN, offset, false); + + /* disable gpio input */ + owl_gpio_update_reg(gpio->base + GPIO_INEN, offset, false); + spin_unlock(&gpio->lock); +} + +static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + u32 val; + + spin_lock(&gpio->lock); + val = readl_relaxed(gpio->base + GPIO_DAT); + spin_unlock(&gpio->lock); + + return !!(val & BIT(offset)); +} + +static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + + spin_lock(&gpio->lock); + owl_gpio_update_reg(gpio->base + GPIO_DAT, offset, value); + spin_unlock(&gpio->lock); +} + +static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + + spin_lock(&gpio->lock); + owl_gpio_update_reg(gpio->base + GPIO_OUTEN, offset, false); + owl_gpio_update_reg(gpio->base + GPIO_INEN, offset, true); + spin_unlock(&gpio->lock); + + return 0; +} + +static int owl_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + + spin_lock(&gpio->lock); + owl_gpio_update_reg(gpio->base + GPIO_INEN, offset, false); + owl_gpio_update_reg(gpio->base + GPIO_OUTEN, offset, true); + owl_gpio_update_reg(gpio->base + GPIO_DAT, offset, value); + spin_unlock(&gpio->lock); + + return 0; +} + +static int owl_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct owl_gpio *gpio; + u32 ngpios; + int ret; + + gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) + return -ENOMEM; + + gpio->base = of_iomap(dev->of_node, 0); + if (IS_ERR(gpio->base)) + return PTR_ERR(gpio->base); + + /* + * Get the number of gpio's for this bank. If none specified, + * then fall back to 32. + */ + ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios); + if (ret) + ngpios = 32; + + spin_lock_init(&gpio->lock); + + gpio->gpio.request = owl_gpio_request; + gpio->gpio.free = owl_gpio_free; + gpio->gpio.get = owl_gpio_get; + gpio->gpio.set = owl_gpio_set; + gpio->gpio.direction_input = owl_gpio_direction_input; + gpio->gpio.direction_output = owl_gpio_direction_output; + + gpio->gpio.base = -1; + gpio->gpio.parent = dev; + gpio->gpio.label = dev_name(dev); + gpio->gpio.ngpio = ngpios; + + platform_set_drvdata(pdev, gpio); + + ret = devm_gpiochip_add_data(dev, &gpio->gpio, gpio); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register gpiochip\n"); + return ret; + } + + return 0; +} + +static const struct of_device_id owl_gpio_of_match[] = { + { .compatible = "actions,s900-gpio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, owl_gpio_of_match); + +static struct platform_driver owl_gpio_driver = { + .driver = { + .name = "owl-gpio", + .of_match_table = owl_gpio_of_match, + }, + .probe = owl_gpio_probe, +}; +module_platform_driver(owl_gpio_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Actions Semi OWL SoCs GPIO driver"); +MODULE_LICENSE("GPL");