From patchwork Sat Apr 2 16:19:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Rigby X-Patchwork-Id: 89455 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 58FD7B6F9E for ; Sun, 3 Apr 2011 02:29:03 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0C0CD2809C; Sat, 2 Apr 2011 18:29:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iYhwjcOS2kIR; Sat, 2 Apr 2011 18:29:01 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B3F01280A6; Sat, 2 Apr 2011 18:29:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ACD592809C for ; Sat, 2 Apr 2011 18:28:58 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4qIanBz3sgkQ for ; Sat, 2 Apr 2011 18:28:58 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pz0-f44.google.com (mail-pz0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id 04939280A6 for ; Sat, 2 Apr 2011 18:28:54 +0200 (CEST) Received: by pzk30 with SMTP id 30so872444pzk.3 for ; Sat, 02 Apr 2011 09:28:52 -0700 (PDT) Received: by 10.142.154.20 with SMTP id b20mr4012400wfe.371.1301761241582; Sat, 02 Apr 2011 09:20:41 -0700 (PDT) Received: from localhost.localdomain (c-76-23-54-220.hsd1.ut.comcast.net [76.23.54.220]) by mx.google.com with ESMTPS id n4sm4619040wfl.14.2011.04.02.09.20.39 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 02 Apr 2011 09:20:40 -0700 (PDT) From: John Rigby To: u-boot@lists.denx.de Date: Sat, 2 Apr 2011 10:19:53 -0600 Message-Id: <1301761196-26072-2-git-send-email-john.rigby@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1300826419-18632-1-git-send-email-john.rigby@linaro.org> References: <1300826419-18632-1-git-send-email-john.rigby@linaro.org> Cc: Rabin Vincent Subject: [U-Boot] [PATCHv2 1/4] p101x: extra init for u8500 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Rabin Vincent empty fifo on init program receive line control register on u8500 Signed-off-by: Rabin Vincent --- v2: no changes drivers/serial/serial_pl01x.c | 10 ++++++++++ drivers/serial/serial_pl01x.h | 4 ++++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 5dfcde8..22ada8f 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -112,6 +112,12 @@ int serial_init (void) unsigned int remainder; unsigned int fraction; + /* Empty RX fifo if necessary */ + if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { + while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) + readl(®s->dr); + } + /* First, disable everything */ writel(0, ®s->pl011_cr); @@ -134,6 +140,10 @@ int serial_init (void) writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN, ®s->pl011_lcrh); +#ifdef CONFIG_U8500 + /* program receive line control register */ + writel(0x70, ®s->pl011_rlcr); +#endif /* Finally, enable the UART */ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE, ®s->pl011_cr); diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h index b670c24..fdd3911 100644 --- a/drivers/serial/serial_pl01x.h +++ b/drivers/serial/serial_pl01x.h @@ -43,7 +43,11 @@ struct pl01x_regs { u32 pl010_lcrl; /* 0x10 Line control register, low byte */ u32 pl010_cr; /* 0x14 Control register */ u32 fr; /* 0x18 Flag register (Read only) */ +#ifdef CONFIG_U8500 + u32 pl011_rlcr; /* 0x1c Receive line control register */ +#else u32 reserved; +#endif u32 ilpr; /* 0x20 IrDA low-power counter register */ u32 pl011_ibrd; /* 0x24 Integer baud rate register */ u32 pl011_fbrd; /* 0x28 Fractional baud rate register */