| Message ID | 20180403061836.3926-8-mylene.josserand@bootlin.com |
|---|---|
| State | New |
| Headers | show |
| Series | Sunxi: Add SMP support on A83T | expand |
Hi Mylène, On 03/04/18 07:18, Mylène Josserand wrote: > The CNTVOFF register from arch timer is uninitialized. > It should be done by the bootloader but it is currently not the case, > even for boot CPU because this SoC is booting in secure mode. > It leads to an random offset value meaning that each CPU will have a > different time, which isn't working very well. > > Add assembly code used for boot CPU and secondary CPU cores to make > sure that the CNTVOFF register is initialized. Because this code can > be used by different platforms, add this assembly file in ARM's common > folder. > > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> > --- > arch/arm/common/Makefile | 1 + > arch/arm/common/smp_cntvoff.S | 35 +++++++++++++++++++++++++++++++++++ > arch/arm/include/asm/smp_cntvoff.h | 8 ++++++++ > 3 files changed, 44 insertions(+) > create mode 100644 arch/arm/common/smp_cntvoff.S > create mode 100644 arch/arm/include/asm/smp_cntvoff.h > > diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile > index 70b4a14ed993..83117deb86c8 100644 > --- a/arch/arm/common/Makefile > +++ b/arch/arm/common/Makefile > @@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o > obj-$(CONFIG_SHARP_LOCOMO) += locomo.o > obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o > obj-$(CONFIG_SHARP_SCOOP) += scoop.o > +obj-$(CONFIG_SMP) += smp_cntvoff.o > obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o > obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o > CFLAGS_REMOVE_mcpm_entry.o = -pg > diff --git a/arch/arm/common/smp_cntvoff.S b/arch/arm/common/smp_cntvoff.S > new file mode 100644 > index 000000000000..65ed199a50fe > --- /dev/null > +++ b/arch/arm/common/smp_cntvoff.S > @@ -0,0 +1,35 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 Chen-Yu Tsai > + * Copyright (c) 2018 Bootlin > + * > + * Chen-Yu Tsai <wens@csie.org> > + * Mylène Josserand <mylene.josserand@bootlin.com> Given that this is literally lifted from shmobile_init_cntvoff, the whole attribution is a bit dubious. > + * > + * SMP support for sunxi based systems with Cortex A7/A15 That's not restricted to sunxi, is it? > + * > + */ > + > +#include <linux/linkage.h> > +#include <asm/assembler.h> > + > +ENTRY(smp_init_cntvoff) The name doesn't quite reflect the usage constraints. This will only work if used from secure, and is UNPREDICTABLE otherwise (see the CPS instruction). Also, the "smp" prefix is quite misleading, as it only affects the current CPU, and not any other. How about secure_cntvoff_init instead? Same thing for the file name. > + .arch armv7-a > + /* > + * CNTVOFF has to be initialized either from non-secure Hypervisor > + * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled > + * then it should be handled by the secure code > + */ > + cps #MON_MODE > + mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */ > + orr r0, r1, #1 > + mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */ > + isb > + mov r0, #0 > + mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */ > + isb > + mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */ > + isb > + cps #SVC_MODE > + ret lr > +ENDPROC(smp_init_cntvoff) > diff --git a/arch/arm/include/asm/smp_cntvoff.h b/arch/arm/include/asm/smp_cntvoff.h > new file mode 100644 > index 000000000000..59a95f7604ee > --- /dev/null > +++ b/arch/arm/include/asm/smp_cntvoff.h > @@ -0,0 +1,8 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +#ifndef __ASMARM_ARCH_CNTVOFF_H > +#define __ASMARM_ARCH_CNTVOFF_H > + > +extern void smp_init_cntvoff(void); > + > +#endif > It'd be good to take this opportunity to refactor the shmobile code. Thanks, M.
Hi Marc, Thank you for the review. On Wed, 4 Apr 2018 14:01:48 +0100 Marc Zyngier <marc.zyngier@arm.com> wrote: > Hi Mylène, > > On 03/04/18 07:18, Mylène Josserand wrote: > > The CNTVOFF register from arch timer is uninitialized. > > It should be done by the bootloader but it is currently not the case, > > even for boot CPU because this SoC is booting in secure mode. > > It leads to an random offset value meaning that each CPU will have a > > different time, which isn't working very well. > > > > Add assembly code used for boot CPU and secondary CPU cores to make > > sure that the CNTVOFF register is initialized. Because this code can > > be used by different platforms, add this assembly file in ARM's common > > folder. > > > > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> > > --- > > arch/arm/common/Makefile | 1 + > > arch/arm/common/smp_cntvoff.S | 35 +++++++++++++++++++++++++++++++++++ > > arch/arm/include/asm/smp_cntvoff.h | 8 ++++++++ > > 3 files changed, 44 insertions(+) > > create mode 100644 arch/arm/common/smp_cntvoff.S > > create mode 100644 arch/arm/include/asm/smp_cntvoff.h > > > > diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile > > index 70b4a14ed993..83117deb86c8 100644 > > --- a/arch/arm/common/Makefile > > +++ b/arch/arm/common/Makefile > > @@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o > > obj-$(CONFIG_SHARP_LOCOMO) += locomo.o > > obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o > > obj-$(CONFIG_SHARP_SCOOP) += scoop.o > > +obj-$(CONFIG_SMP) += smp_cntvoff.o > > obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o > > obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o > > CFLAGS_REMOVE_mcpm_entry.o = -pg > > diff --git a/arch/arm/common/smp_cntvoff.S b/arch/arm/common/smp_cntvoff.S > > new file mode 100644 > > index 000000000000..65ed199a50fe > > --- /dev/null > > +++ b/arch/arm/common/smp_cntvoff.S > > @@ -0,0 +1,35 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2018 Chen-Yu Tsai > > + * Copyright (c) 2018 Bootlin > > + * > > + * Chen-Yu Tsai <wens@csie.org> > > + * Mylène Josserand <mylene.josserand@bootlin.com> > > Given that this is literally lifted from shmobile_init_cntvoff, the > whole attribution is a bit dubious. Yes, sorry, I will fix that. > > > + * > > + * SMP support for sunxi based systems with Cortex A7/A15 > > That's not restricted to sunxi, is it? Nope, I will update this line too (bad copy-paste from sunxi/headsmp.S...) > > > + * > > + */ > > + > > +#include <linux/linkage.h> > > +#include <asm/assembler.h> > > + > > +ENTRY(smp_init_cntvoff) > > The name doesn't quite reflect the usage constraints. This will only > work if used from secure, and is UNPREDICTABLE otherwise (see the CPS > instruction). Also, the "smp" prefix is quite misleading, as it only > affects the current CPU, and not any other. > > How about secure_cntvoff_init instead? Same thing for the file name. Sure, this name is fine for me. > > > + .arch armv7-a > > + /* > > + * CNTVOFF has to be initialized either from non-secure Hypervisor > > + * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled > > + * then it should be handled by the secure code > > + */ > > + cps #MON_MODE > > + mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */ > > + orr r0, r1, #1 > > + mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */ > > + isb > > + mov r0, #0 > > + mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */ > > + isb > > + mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */ > > + isb > > + cps #SVC_MODE > > + ret lr > > +ENDPROC(smp_init_cntvoff) > > diff --git a/arch/arm/include/asm/smp_cntvoff.h b/arch/arm/include/asm/smp_cntvoff.h > > new file mode 100644 > > index 000000000000..59a95f7604ee > > --- /dev/null > > +++ b/arch/arm/include/asm/smp_cntvoff.h > > @@ -0,0 +1,8 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > + > > +#ifndef __ASMARM_ARCH_CNTVOFF_H > > +#define __ASMARM_ARCH_CNTVOFF_H > > + > > +extern void smp_init_cntvoff(void); > > + > > +#endif > > > > It'd be good to take this opportunity to refactor the shmobile code. I can do it in this series but I do not have any shmobile platforms so I will not be able to test my modifications (only compilation). If someone can test it for me (who?), it is okay for me to refactor this code :) Best regards,
On Wed, 04 Apr 2018 14:59:09 +0100, Mylène Josserand wrote: > > It'd be good to take this opportunity to refactor the shmobile code. > > I can do it in this series but I do not have any shmobile platforms so > I will not be able to test my modifications (only compilation). > > If someone can test it for me (who?), it is okay for me to refactor this > code :) I guess you could Cc the shmobile folks (Geert Uytterhoeven, Simon Horman), and get them to review/test the changes. Thanks, M.
On Wed, Apr 4, 2018 at 4:30 PM, Marc Zyngier <marc.zyngier@arm.com> wrote: > On Wed, 04 Apr 2018 14:59:09 +0100, > Mylčne Josserand wrote: [Marc: stuck in ISO-8859-1? ;-] >> > It'd be good to take this opportunity to refactor the shmobile code. >> >> I can do it in this series but I do not have any shmobile platforms so >> I will not be able to test my modifications (only compilation). >> >> If someone can test it for me (who?), it is okay for me to refactor this >> code :) > > I guess you could Cc the shmobile folks (Geert Uytterhoeven, Simon > Horman), and get them to review/test the changes. Correct. I can test on a remote R-Car E2 ALT board that needs it. P.S. Interestingly, none of the Renesas CA15 SoCs seem to suffer from it, only CA7. Gr{oetje,eeting}s, Geert
On 09/04/18 09:24, Geert Uytterhoeven wrote: > On Wed, Apr 4, 2018 at 4:30 PM, Marc Zyngier <marc.zyngier@arm.com> wrote: >> On Wed, 04 Apr 2018 14:59:09 +0100, >> Mylčne Josserand wrote: > > [Marc: stuck in ISO-8859-1? ;-] I have no idea what Wanderlust does (that's what I use on my laptop). But Thunderbird definitely interprets the original posting as 'è', which should work with a 8859-1. I need to have a look at how to get UTF-8 to be the default... (I hate email clients). > >>>> It'd be good to take this opportunity to refactor the shmobile code. >>> >>> I can do it in this series but I do not have any shmobile platforms so >>> I will not be able to test my modifications (only compilation). >>> >>> If someone can test it for me (who?), it is okay for me to refactor this >>> code :) >> >> I guess you could Cc the shmobile folks (Geert Uytterhoeven, Simon >> Horman), and get them to review/test the changes. > > Correct. I can test on a remote R-Car E2 ALT board that needs it. > > P.S. Interestingly, none of the Renesas CA15 SoCs seem to suffer from it, > only CA7. I suspect A15 has the courtesy of resetting CNTVOFF to zero, and A7 doesn't. But the letter of the architecture is that it has an "UNKNOWN reset value". Thanks, M.
Hello, On Mon, 9 Apr 2018 10:24:41 +0200 Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Wed, Apr 4, 2018 at 4:30 PM, Marc Zyngier <marc.zyngier@arm.com> wrote: > > On Wed, 04 Apr 2018 14:59:09 +0100, > > Mylčne Josserand wrote: > > [Marc: stuck in ISO-8859-1? ;-] > > >> > It'd be good to take this opportunity to refactor the shmobile code. > >> > >> I can do it in this series but I do not have any shmobile platforms so > >> I will not be able to test my modifications (only compilation). > >> > >> If someone can test it for me (who?), it is okay for me to refactor this > >> code :) > > > > I guess you could Cc the shmobile folks (Geert Uytterhoeven, Simon > > Horman), and get them to review/test the changes. > > Correct. I can test on a remote R-Car E2 ALT board that needs it. Great, thank you! I will add you in CC in my next version, then. Best regards, Mylène
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 70b4a14ed993..83117deb86c8 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o obj-$(CONFIG_SHARP_LOCOMO) += locomo.o obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o obj-$(CONFIG_SHARP_SCOOP) += scoop.o +obj-$(CONFIG_SMP) += smp_cntvoff.o obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o CFLAGS_REMOVE_mcpm_entry.o = -pg diff --git a/arch/arm/common/smp_cntvoff.S b/arch/arm/common/smp_cntvoff.S new file mode 100644 index 000000000000..65ed199a50fe --- /dev/null +++ b/arch/arm/common/smp_cntvoff.S @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Chen-Yu Tsai + * Copyright (c) 2018 Bootlin + * + * Chen-Yu Tsai <wens@csie.org> + * Mylène Josserand <mylene.josserand@bootlin.com> + * + * SMP support for sunxi based systems with Cortex A7/A15 + * + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> + +ENTRY(smp_init_cntvoff) + .arch armv7-a + /* + * CNTVOFF has to be initialized either from non-secure Hypervisor + * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled + * then it should be handled by the secure code + */ + cps #MON_MODE + mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */ + orr r0, r1, #1 + mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */ + isb + mov r0, #0 + mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */ + isb + mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */ + isb + cps #SVC_MODE + ret lr +ENDPROC(smp_init_cntvoff) diff --git a/arch/arm/include/asm/smp_cntvoff.h b/arch/arm/include/asm/smp_cntvoff.h new file mode 100644 index 000000000000..59a95f7604ee --- /dev/null +++ b/arch/arm/include/asm/smp_cntvoff.h @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __ASMARM_ARCH_CNTVOFF_H +#define __ASMARM_ARCH_CNTVOFF_H + +extern void smp_init_cntvoff(void); + +#endif
The CNTVOFF register from arch timer is uninitialized. It should be done by the bootloader but it is currently not the case, even for boot CPU because this SoC is booting in secure mode. It leads to an random offset value meaning that each CPU will have a different time, which isn't working very well. Add assembly code used for boot CPU and secondary CPU cores to make sure that the CNTVOFF register is initialized. Because this code can be used by different platforms, add this assembly file in ARM's common folder. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> --- arch/arm/common/Makefile | 1 + arch/arm/common/smp_cntvoff.S | 35 +++++++++++++++++++++++++++++++++++ arch/arm/include/asm/smp_cntvoff.h | 8 ++++++++ 3 files changed, 44 insertions(+) create mode 100644 arch/arm/common/smp_cntvoff.S create mode 100644 arch/arm/include/asm/smp_cntvoff.h