From patchwork Fri Apr 1 07:16:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Schocher X-Patchwork-Id: 89224 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A80F5B6F8D for ; Fri, 1 Apr 2011 18:25:34 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AF194280D8; Fri, 1 Apr 2011 09:24:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mHQS-KFPGT4P; Fri, 1 Apr 2011 09:24:26 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ACB5C280D9; Fri, 1 Apr 2011 09:23:24 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ADC0528098 for ; Fri, 1 Apr 2011 09:23:16 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aH-2O7ICZlSR for ; Fri, 1 Apr 2011 09:23:15 +0200 (CEST) X-policyd-weight: IN_SBL_XBL_SPAMHAUS=4.35 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from pollux.denx.de (p4FF073FC.dip.t-dialin.net [79.240.115.252]) by theia.denx.de (Postfix) with ESMTP id 9831028094 for ; Fri, 1 Apr 2011 09:23:09 +0200 (CEST) Received: by pollux.denx.de (Postfix, from userid 515) id CD44E1801580D; Fri, 1 Apr 2011 09:16:37 +0200 (CEST) From: Heiko Schocher To: u-boot@lists.denx.de Date: Fri, 1 Apr 2011 09:16:19 +0200 Message-Id: <1301642195-15280-8-git-send-email-hs@denx.de> X-Mailer: git-send-email 1.7.4 In-Reply-To: <1301642195-15280-1-git-send-email-hs@denx.de> References: <1299591018-8944-1-git-send-email-hs@denx.de> <1301642195-15280-1-git-send-email-hs@denx.de> In-Reply-To: <1299591018-8944-1-git-send-email-hs@denx.de> References: <1299591018-8944-1-git-send-email-hs@denx.de> Cc: Valentin Longchamp , Kim Phillips , Lukas Roggli , Holger Brunck , Heiko Schocher Subject: [U-Boot] [PATCH v4 07/23] mpc832x: add support for mpc8321 based tuxa1 board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This board is similar to suvd3 board. So most initialisation topics are taken from suvd3 (UART1, Ethernet, piggy PHY, flash, ram) only the application specific chip selects differ. Signed-off-by: Lukas Roggli Signed-off-by: Holger Brunck Signed-off-by: Heiko Schocher cc: Kim Phillips cc: Valentin Longchamp Signed-off-by: Kim Phillips --- Changes for v2: - fix checkpatch.pl errors and warnings Changes for v3: - rebased only Changes for v4: - addressed comment from Kim Phillips: - Codingsytle changes - removed CONFIG_SYS_SICRH define, as it not exists on 832x MAINTAINERS | 1 + boards.cfg | 1 + include/configs/tuxa1.h | 233 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 235 insertions(+), 0 deletions(-) create mode 100644 include/configs/tuxa1.h diff --git a/MAINTAINERS b/MAINTAINERS index 75b7343..801e4dd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,6 +434,7 @@ Heiko Schocher sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) suvd3 MPC8321 + tuxa1 MPC8321 uc101 MPC5200 ve8313 MPC8313 diff --git a/boards.cfg b/boards.cfg index dc583ba..ed5e0e7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -476,6 +476,7 @@ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP suvd3 powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc +tuxa1 powerpc mpc83xx km83xx keymile sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h new file mode 100644 index 0000000..ba3570b --- /dev/null +++ b/include/configs/tuxa1.h @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010 + * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC832x /* MPC832x CPU specific */ +#define CONFIG_TUXA1 /* TUXA1 board specific */ +#define CONFIG_HOSTNAME tuxa1 +#define CONFIG_KM_BOARD_NAME "tuxa1" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_2T_EN | \ + SDRAM_CFG_SREN) +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (6 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_PIGGY_BASE 0xE8000000 +#define CONFIG_SYS_PIGGY_SIZE 128 +#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */ +#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */ +#define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */ + + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local GPCM 8 bit 256MB LPXF + * 3 Local GPCM 8 bit 256MB PINC2 + * + */ + +/* + * LPXF on the local bus CS2 + * Window base at flash base + * Window size: 256 MB + */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + (OR_GPCM_TRLX & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_EAD) +/* + * PINC2 on the local bus CS3 + * Access window base at PINC2 base + * Window size: 256 MB + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \ + OR_GPCM_CSNT | \ + (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \ + (~OR_GPCM_XACS)) | /* XACS = 0 */ \ + (OR_GPCM_SCY_2 & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_TRLX) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +/* + * MMU Setup + */ +/* LPXF: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ + +/* PINC2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +#endif /* __CONFIG_H */