From patchwork Tue Mar 27 14:15:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 891601 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 409YBM3Qvwz9s0n for ; Wed, 28 Mar 2018 01:22:33 +1100 (AEDT) Received: from localhost ([::1]:34567 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0pUc-0001wm-7t for incoming@patchwork.ozlabs.org; Tue, 27 Mar 2018 10:22:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45868) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0pOS-0003MJ-8E for qemu-devel@nongnu.org; Tue, 27 Mar 2018 10:16:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0pOM-0006md-7k for qemu-devel@nongnu.org; Tue, 27 Mar 2018 10:16:08 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:48740 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f0pOE-0006fO-S0; Tue, 27 Mar 2018 10:15:54 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6CBFB40704A4; Tue, 27 Mar 2018 14:15:54 +0000 (UTC) Received: from localhost.localdomain.com (ovpn-116-135.ams2.redhat.com [10.36.116.135]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2C2016F9E6; Tue, 27 Mar 2018 14:15:50 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Date: Tue, 27 Mar 2018 16:15:20 +0200 Message-Id: <1522160122-10744-7-git-send-email-eric.auger@redhat.com> In-Reply-To: <1522160122-10744-1-git-send-email-eric.auger@redhat.com> References: <1522160122-10744-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Tue, 27 Mar 2018 14:15:54 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Tue, 27 Mar 2018 14:15:54 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'eric.auger@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [RFC 6/8] hw/arm/virt: Allow GICv3 DT node with multiple redistributor regions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, marc.zyngier@arm.com, drjones@redhat.com, cdall@kernel.org, zhaoshenglong@huawei.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This patch adds the GICState handle in the virtual machine state and allows to create a GIC device tree node advertising multiple redistributor regions. There is one range per distributor region following the GIC distributor. Please refer to kernel documentation for further details: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt Signed-off-by: Eric Auger --- hw/arm/virt.c | 32 +++++++++++++++++++++++++++----- include/hw/arm/virt.h | 2 ++ 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 0eef6aa..8258f6f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -401,13 +401,34 @@ static void fdt_add_gic_node(VirtMachineState *vms) qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); if (vms->gic_version == 3) { + GICv3State *s = (GICv3State *)vms->gic; + uint64_t num_reg_values; + uint64_t *regs; + int r; + qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", "arm,gic-v3"); - qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", - 2, vms->memmap[VIRT_GIC_DIST].base, - 2, vms->memmap[VIRT_GIC_DIST].size, - 2, vms->memmap[VIRT_GIC_REDIST].base, - 2, vms->memmap[VIRT_GIC_REDIST].size); + + num_reg_values = 4 * (s->nb_redist_regions + 1); + regs = g_new0(uint64_t, num_reg_values); + qemu_fdt_setprop_cell(vms->fdt, "/intc", "#redistributor-regions", + s->nb_redist_regions); + regs[0] = 2; + regs[1] = vms->memmap[VIRT_GIC_DIST].base; + regs[2] = 2; + regs[3] = vms->memmap[VIRT_GIC_DIST].size; + + for (r = 1; r <= s->nb_redist_regions; r++) { + regs[4 * r] = 2; + regs[4 * r + 1] = s->redist_region[r - 1].base; + regs[4 * r + 2] = 2; + /* count redistributors of 2 x 64kB pages */ + regs[4 * r + 3] = (uint64_t)s->redist_region[r - 1].count << 17; + } + qemu_fdt_setprop_sized_cells_from_array(vms->fdt, "/intc", "reg", + num_reg_values / 2, regs); + g_free(regs); + if (vms->virt) { qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ, @@ -513,6 +534,7 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic) gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); gicdev = qdev_create(NULL, gictype); + vms->gic = (GICState *)gicdev; qdev_prop_set_uint32(gicdev, "revision", type); qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); /* Note that the num-irq property counts both internal and external diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index ba0c1a4..d168291 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -35,6 +35,7 @@ #include "qemu/notify.h" #include "hw/boards.h" #include "hw/arm/arm.h" +#include "hw/intc/arm_gic_common.h" #define NUM_GICV2M_SPIS 64 #define NUM_VIRTIO_TRANSPORTS 32 @@ -92,6 +93,7 @@ typedef struct { MachineState parent; Notifier machine_done; FWCfgState *fw_cfg; + GICState *gic; bool secure; bool highmem; bool its;