From patchwork Tue Mar 27 14:15:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 891593 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 409Y3p3MSSz9s1S for ; Wed, 28 Mar 2018 01:16:52 +1100 (AEDT) Received: from localhost ([::1]:34529 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0pP7-0003FW-8Q for incoming@patchwork.ozlabs.org; Tue, 27 Mar 2018 10:16:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45469) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0pO6-000324-Sa for qemu-devel@nongnu.org; Tue, 27 Mar 2018 10:15:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0pO5-0006W8-NF for qemu-devel@nongnu.org; Tue, 27 Mar 2018 10:15:46 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:51248 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f0pO2-0006OH-3e; Tue, 27 Mar 2018 10:15:42 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 9524D722C6; Tue, 27 Mar 2018 14:15:40 +0000 (UTC) Received: from localhost.localdomain.com (ovpn-116-135.ams2.redhat.com [10.36.116.135]) by smtp.corp.redhat.com (Postfix) with ESMTP id B14CB8442C; Tue, 27 Mar 2018 14:15:38 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Date: Tue, 27 Mar 2018 16:15:16 +0200 Message-Id: <1522160122-10744-3-git-send-email-eric.auger@redhat.com> In-Reply-To: <1522160122-10744-1-git-send-email-eric.auger@redhat.com> References: <1522160122-10744-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Tue, 27 Mar 2018 14:15:40 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Tue, 27 Mar 2018 14:15:40 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'eric.auger@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [RFC 2/8] hw/intc/arm_gicv3: Use an array of redistributor regions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, marc.zyngier@arm.com, drjones@redhat.com, cdall@kernel.org, zhaoshenglong@huawei.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In the prospect to support multiple redistributor regions, let's introduce a GICv3RDISTRegion struct datatype and a statically sized array of those. For the time being, only one redistributor region is used. Signed-off-by: Eric Auger --- hw/intc/arm_gicv3_common.c | 5 +++-- hw/intc/arm_gicv3_kvm.c | 3 ++- include/hw/intc/arm_gicv3_common.h | 13 ++++++++++++- 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 7b54d52..cb4ee0e 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -199,11 +199,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, "gicv3_dist", 0x10000); - memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s, + memory_region_init_io(&s->redist_region[0].mr, OBJECT(s), + ops ? &ops[1] : NULL, s, "gicv3_redist", 0x20000 * s->num_cpu); sysbus_init_mmio(sbd, &s->iomem_dist); - sysbus_init_mmio(sbd, &s->iomem_redist); + sysbus_init_mmio(sbd, &s->redist_region[0].mr); } static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index ec37177..a07bc55 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -755,7 +755,8 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd); - kvm_arm_register_device(&s->iomem_redist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, + kvm_arm_register_device(&s->redist_region[0].mr, -1, + KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd); if (kvm_has_gsi_routing()) { diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index bccdfe1..3cf132f 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -137,12 +137,20 @@ typedef struct GICv3CPUState GICv3CPUState; #define GICV3_S 0 #define GICV3_NS 1 +#define GICV3_MAX_RDIST_REGIONS 8 + typedef struct { int irq; uint8_t prio; int grp; } PendingIrq; +typedef struct GICv3RDISTRegion { + hwaddr base; + uint32_t count; /* number or redistributors */ + MemoryRegion mr; +} GICv3RDISTRegion ; + struct GICv3CPUState { GICv3State *gic; CPUState *cpu; @@ -210,7 +218,8 @@ struct GICv3State { /*< public >*/ MemoryRegion iomem_dist; /* Distributor */ - MemoryRegion iomem_redist; /* Redistributors */ + GICv3RDISTRegion redist_region[GICV3_MAX_RDIST_REGIONS]; + uint32_t nb_redist_regions; uint32_t num_cpu; uint32_t num_irq; @@ -288,6 +297,8 @@ typedef struct ARMGICv3CommonClass { void (*pre_save)(GICv3State *s); void (*post_load)(GICv3State *s); + /* register an RDIST region at @base, containing @pfns 64kB pages */ + int (*register_redist_region)(GICv3State *s, hwaddr base, uint32_t pfns); } ARMGICv3CommonClass; void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,