| Message ID | 1522159043-1155-1-git-send-email-stefan@olimex.com |
|---|---|
| State | Accepted |
| Commit | 4744d81cc0dbe238bd4d8cd88c1c71022bffa621 |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | [U-Boot,1/1] sunxi: mmc: Fix phase delays | expand |
On Tue, Mar 27, 2018 at 04:57:23PM +0300, Stefan Mavrodiev wrote: > U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where > PLL5 is used, with clock rates respectively 600MHz and 768MHz. > Thus there are different phase degree steps - 24 for the kernel and > 30 for u-boot. > > In the kernel driver the phase is set 90 deg for output and 120 for > sample. Dividing by 30 will result values 3 and 4. Those are the > values set in the u-boot driver. > > However, the condition defining delays is wrong. MMC core driver > requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but > phase is set 30 deg for output and 120 deg for sample. > > Apparently this works for most cards. > On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains > about it. Maybe there is other boards with similar problem? > So the fix is to match delays for both u-boot and kernel. > > Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Maxime
On Thu, Mar 29, 2018 at 6:52 PM, Maxime Ripard <maxime.ripard@bootlin.com> wrote: > On Tue, Mar 27, 2018 at 04:57:23PM +0300, Stefan Mavrodiev wrote: >> U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where >> PLL5 is used, with clock rates respectively 600MHz and 768MHz. >> Thus there are different phase degree steps - 24 for the kernel and >> 30 for u-boot. >> >> In the kernel driver the phase is set 90 deg for output and 120 for >> sample. Dividing by 30 will result values 3 and 4. Those are the >> values set in the u-boot driver. >> >> However, the condition defining delays is wrong. MMC core driver >> requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but >> phase is set 30 deg for output and 120 deg for sample. >> >> Apparently this works for most cards. >> On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains >> about it. Maybe there is other boards with similar problem? >> So the fix is to match delays for both u-boot and kernel. >> >> Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> > > Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Applied to u-boot-sunxi/master
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 4edb4be..be55dc4 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -146,19 +146,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) oclk_dly = 0; sclk_dly = 5; #ifdef CONFIG_MACH_SUN9I - } else if (hz <= 50000000) { + } else if (hz <= 52000000) { oclk_dly = 5; sclk_dly = 4; } else { - /* hz > 50000000 */ + /* hz > 52000000 */ oclk_dly = 2; sclk_dly = 4; #else - } else if (hz <= 50000000) { + } else if (hz <= 52000000) { oclk_dly = 3; sclk_dly = 4; } else { - /* hz > 50000000 */ + /* hz > 52000000 */ oclk_dly = 1; sclk_dly = 4; #endif
U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where PLL5 is used, with clock rates respectively 600MHz and 768MHz. Thus there are different phase degree steps - 24 for the kernel and 30 for u-boot. In the kernel driver the phase is set 90 deg for output and 120 for sample. Dividing by 30 will result values 3 and 4. Those are the values set in the u-boot driver. However, the condition defining delays is wrong. MMC core driver requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but phase is set 30 deg for output and 120 deg for sample. Apparently this works for most cards. On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains about it. Maybe there is other boards with similar problem? So the fix is to match delays for both u-boot and kernel. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> --- drivers/mmc/sunxi_mmc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)