Index: gcc/config/rs6000/vector.md
===================================================================
--- gcc/config/rs6000/vector.md	(revision 171787)
+++ gcc/config/rs6000/vector.md	(working copy)
@@ -871,8 +871,8 @@ (define_expand "vec_realign_load_<mode>"
 ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
 ;; since the load already handles it.
 (define_expand "movmisalign<mode>"
- [(set (match_operand:VEC_N 0 "vfloat_operand" "")
-       (match_operand:VEC_N 1 "vfloat_operand" ""))]
+ [(set (match_operand:VEC_N 0 "nonimmediate_operand" "")
+       (match_operand:VEC_N 1 "any_operand" ""))]
  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
  "")
 
Index: gcc/config/rs6000/altivec.md
===================================================================
--- gcc/config/rs6000/altivec.md	(revision 171787)
+++ gcc/config/rs6000/altivec.md	(working copy)
@@ -2422,7 +2422,7 @@ (define_insn "altivec_stvrxl"
 
 (define_expand "vec_extract_evenv4si"
  [(set (match_operand:V4SI 0 "register_operand" "")
-        (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
+        (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "")
                       (match_operand:V4SI 2 "register_operand" "")]
 		      UNSPEC_EXTEVEN_V4SI))]
   "TARGET_ALTIVEC"
@@ -2455,7 +2455,7 @@ (define_expand "vec_extract_evenv4si"
 
 (define_expand "vec_extract_evenv4sf"
  [(set (match_operand:V4SF 0 "register_operand" "")
-        (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
+        (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
                       (match_operand:V4SF 2 "register_operand" "")]
                       UNSPEC_EXTEVEN_V4SF))]
   "TARGET_ALTIVEC"
@@ -2487,7 +2487,7 @@ (define_expand "vec_extract_evenv4sf"
 }")
 
 (define_expand "vec_extract_evenv8hi"
- [(set (match_operand:V4SI 0 "register_operand" "")
+ [(set (match_operand:V8HI 0 "register_operand" "")
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
                       (match_operand:V8HI 2 "register_operand" "")]
                       UNSPEC_EXTEVEN_V8HI))]
@@ -2520,9 +2520,9 @@ (define_expand "vec_extract_evenv8hi"
 }")
 
 (define_expand "vec_extract_evenv16qi"
- [(set (match_operand:V4SI 0 "register_operand" "")
-        (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "")
-                      (match_operand:V16QI 2 "register_operand" "")]
+ [(set (match_operand:V16QI 0 "register_operand" "")
+        (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
+                       (match_operand:V16QI 2 "register_operand" "")]
                       UNSPEC_EXTEVEN_V16QI))]
   "TARGET_ALTIVEC"
   "
@@ -2554,7 +2554,7 @@ (define_expand "vec_extract_evenv16qi"
 
 (define_expand "vec_extract_oddv4si"
  [(set (match_operand:V4SI 0 "register_operand" "")
-        (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
+        (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "")
                       (match_operand:V4SI 2 "register_operand" "")]
                       UNSPEC_EXTODD_V4SI))]
   "TARGET_ALTIVEC"
@@ -2587,7 +2587,7 @@ (define_expand "vec_extract_oddv4si"
 
 (define_expand "vec_extract_oddv4sf"
  [(set (match_operand:V4SF 0 "register_operand" "")
-        (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
+        (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
                       (match_operand:V4SF 2 "register_operand" "")]
                       UNSPEC_EXTODD_V4SF))]
   "TARGET_ALTIVEC"