Patchwork [U-Boot,1/2] ARMV7: Adding support for Samsung SMDKV310 Board

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Submitter Chander Kashyap
Date March 31, 2011, 9:14 a.m.
Message ID <1301562892-13133-2-git-send-email-chander.kashyap@linaro.org>
Download mbox | patch
Permalink /patch/89050/
State Changes Requested
Delegated to: Minkyu Kang
Headers show

Comments

Chander Kashyap - March 31, 2011, 9:14 a.m.
SMDKV310 board is based on Samsung S5PV310 SOC. This SOC is very much
similar to S5PC210.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
---
 board/samsung/smdkv310/Makefile        |   46 +++
 board/samsung/smdkv310/config.mk       |    1 +
 board/samsung/smdkv310/lowlevel_init.S |  549 +++++++++++++++++++++++++++
 board/samsung/smdkv310/mem_setup.S     |  632 ++++++++++++++++++++++++++++++++
 board/samsung/smdkv310/smdkv310.c      |  138 +++++++
 boards.cfg                             |    1 +
 include/configs/smdkv310.h             |  199 ++++++++++
 7 files changed, 1566 insertions(+), 0 deletions(-)
 create mode 100644 board/samsung/smdkv310/Makefile
 create mode 100644 board/samsung/smdkv310/config.mk
 create mode 100644 board/samsung/smdkv310/lowlevel_init.S
 create mode 100644 board/samsung/smdkv310/mem_setup.S
 create mode 100644 board/samsung/smdkv310/smdkv310.c
 create mode 100644 include/configs/smdkv310.h

--
1.7.1
Minkyu Kang - April 1, 2011, 7:22 a.m.
Dear Chander Kashyap,

On 31 March 2011 18:14, Chander Kashyap <chander.kashyap@linaro.org> wrote:
> SMDKV310 board is based on Samsung S5PV310 SOC. This SOC is very much
> similar to S5PC210.
>
> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
> Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
> ---
>  board/samsung/smdkv310/Makefile        |   46 +++
>  board/samsung/smdkv310/config.mk       |    1 +
>  board/samsung/smdkv310/lowlevel_init.S |  549 +++++++++++++++++++++++++++
>  board/samsung/smdkv310/mem_setup.S     |  632 ++++++++++++++++++++++++++++++++
>  board/samsung/smdkv310/smdkv310.c      |  138 +++++++
>  boards.cfg                             |    1 +
>  include/configs/smdkv310.h             |  199 ++++++++++
>  7 files changed, 1566 insertions(+), 0 deletions(-)
>  create mode 100644 board/samsung/smdkv310/Makefile
>  create mode 100644 board/samsung/smdkv310/config.mk
>  create mode 100644 board/samsung/smdkv310/lowlevel_init.S
>  create mode 100644 board/samsung/smdkv310/mem_setup.S
>  create mode 100644 board/samsung/smdkv310/smdkv310.c
>  create mode 100644 include/configs/smdkv310.h

You missing MAINTAINER entry.

> diff --git a/board/samsung/smdkv310/config.mk b/board/samsung/smdkv310/config.mk
> new file mode 100644
> index 0000000..19b9e2f
> --- /dev/null
> +++ b/board/samsung/smdkv310/config.mk
> @@ -0,0 +1 @@
> +CONFIG_SYS_TEXT_BASE = 0x43e00000

Please remove this file.
And move this define to config file.

> diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S
> new file mode 100644
> index 0000000..ead12b2
> --- /dev/null
> +++ b/board/samsung/smdkv310/lowlevel_init.S
> +#define MEM_DLLl_ON
> +

please remove this space.

> +
> +_TEXT_BASE:
> +       .word   CONFIG_SYS_TEXT_BASE
> +
> +       .globl lowlevel_init
> +lowlevel_init:
> +       push    {lr}

ditto.

> +
> +
> +       /* r5 has always zero */
> +       mov     r5, #0
> +
> +       ldr     r7, =S5PC210_GPIO_PART1_BASE
> +       ldr     r6, =S5PC210_GPIO_PART2_BASE
> +
> +       /* check reset status  */
> +       ldr     r0, =(S5PC210_POWER_BASE + 0x81C)       @ INFORM7
> +        ldr     r1, [r0]
> +
> +       /* AFTR wakeup reset */
> +       ldr     r2, =S5P_CHECK_DIDLE
> +       cmp     r1, r2
> +       beq     exit_wakeup
> +
> +       /* Sleep wakeup reset */
> +       ldr     r2, =S5P_CHECK_SLEEP
> +       cmp     r1, r2
> +       beq     wakeup_reset
> +
> +       /* when we already run in ram, we don't need to relocate U-Boot.
> +        * and actually, memory controller must be configured before U-Boot
> +        * is running in ram.
> +        */

We don't allow this comment style.
Please check it.
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=Documentation/CodingStyle

> +       ldr     r0, =0x00ffffff         /* r0 <- Mask Bits*/
> +       bic     r1, pc, r0              /* pc <- current addr of code */
> +                                       /* r1 <- unmasked bits of pc */
> +
> +       ldr     r2, _TEXT_BASE          /* r2 <- original base addr in ram */
> +       bic     r2, r2, r0              /* r2 <- unmasked bits of r2*/
> +       cmp     r1, r2                  /* compare r1, r2 */
> +       beq     1f                      /* r0 == r1 then skip sdram init */
> +
> +       /* init system clock */
> +       bl system_clock_init
> +
> +       /* Memory initialize */
> +       bl mem_ctrl_asm_init

Is it OK that memory initialize on u-boot?
Maybe only do on mmc spl?

> +
> +1:
> +       /* for UART */
> +       bl uart_asm_init
> +       bl tzpc_init
> +       pop     {pc}
> +
> +wakeup_reset:
> +       bl system_clock_init
> +       bl mem_ctrl_asm_init
> +       bl tzpc_init
> +
> +exit_wakeup:
> +       /*Load return address and jump to kernel*/
> +       ldr     r0, =(S5PC210_POWER_BASE + 0x800)       @ INFORM0
> +
> +       /* r1 = physical address of s5pc210_cpu_resume function */
> +       ldr     r1, [r0]
> +
> +       /* Jump to kernel*/
> +       mov     pc, r1
> +       nop
> +       nop
> +
> +/*
> + * system_clock_init: Initialize core clock and bus clock.
> + * void system_clock_init(void)
> + */
> +system_clock_init:
> +       push    {lr}
> +       ldr     r0, =S5PC210_CLOCK_BASE
> +
> +       /* APLL(1), MPLL(1), CORE(0), HPM(0) */
> +       ldr     r1, =0x0101
> +       ldr     r2, =0x14200                    @CLK_SRC_CPU
> +       str     r1, [r0, r2]
> +
> +       /* wait ?us */
> +       mov     r1, #0x10000
> +1:     subs    r1, r1, #1
> +       bne     1b
> +
> +       ldr     r1, =0x0110
> +       ldr     r2, =0x0C210                    @CLK_SRC_TOP0
> +       str     r1, [r0, r2]
> +
> +       ldr     r1, =0x00
> +       ldr     r2, =0x0C214                    @CLK_SRC_TOP1_OFFSET
> +       str     r1, [r0, r2]
> +
> +       /* DMC */
> +       ldr     r1, =0x00
> +       ldr     r2, =0x10200                    @CLK_SRC_DMC_OFFSET
> +       str     r1, [r0, r2]
> +
> +       /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
> +
> +       ldr     r1, =0x066666
> +       ldr     r2, =0x0C240                    @ CLK_SRC_FSYS
> +       str     r1, [r0, r2]
> +
> +       /*CLK_SRC_LEFTBUS */
> +       ldr     r1, =0x00
> +       ldr     r2, =0x04200                    @CLK_SRC_LEFTBUS_OFFSET
> +       str     r1, [r0, r2]
> +
> +       /*CLK_SRC_RIGHTBUS */
> +       ldr     r1, =0x00
> +       ldr     r2, =0x08200                    @CLK_SRC_RIGHTBUS_OFFSET
> +       str     r1, [r0, r2]
> +
> +       /* UART[0:4], PWM: SCLKMPLL(6) */
> +       ldr     r1, =0x06666666
> +       ldr     r2, =0x0C250                    @CLK_SRC_PERIL0_OFFSET
> +       str     r1, [r0, r2]
> +
> +       /* wait ?us */
> +       mov     r1, #0x10000
> +4:     subs    r1, r1, #1
> +       bne     4b
> +
> +       /* CLK_DIV_CPU0:
> +               PCLK_DBG_RATIO[20]      0x1
> +               ATB_RATIO[16]           0x3
> +               PERIPH_RATIO[12]        0x3
> +               COREM1_RATIO[8]         0x7
> +               COREM0_RATIO[4]         0x3
> +       */

Check the style.

> +       ldr     r1, =0x0133730
> +       ldr     r2, =0x14500                    @CLK_DIV_CPU0_OFFSET
> +       str     r1, [r0, r2]
> +
> +       /*      CLK_DIV_CPU1
> +               COPY_RATIO [0]          0x3
> +       */

ditto.

> diff --git a/board/samsung/smdkv310/mem_setup.S b/board/samsung/smdkv310/mem_setup.S
> new file mode 100644
> index 0000000..3ff486c
> --- /dev/null
> +++ b/board/samsung/smdkv310/mem_setup.S
> @@ -0,0 +1,632 @@
> +/*
> + * Memory setup for SMDKV310 board based on S5PC210
> + *
> + * Copyright (C) 2011 Samsung Electronics
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +
> +#define SET_MIU
> +
> +#define MEM_DLL
> +
> +#ifdef CONFIG_CLK_800_330_165
> +#define DRAM_CLK_330
> +#endif
> +#ifdef CONFIG_CLK_1000_200_200
> +#define DRAM_CLK_200
> +#endif
> +#ifdef CONFIG_CLK_1000_330_165
> +#define DRAM_CLK_330
> +#endif
> +#ifdef CONFIG_CLK_1000_400_200
> +#define DRAM_CLK_400
> +#endif
> +
> +       .globl mem_ctrl_asm_init
> +mem_ctrl_asm_init:
> +
> +       /* Async bridge configuration at CPU_core */
> +       /* 1: half_sync */
> +       /* 0: full_sync */
> +       ldr r0, =0x10010350
> +       mov r1, #1
> +       str r1, [r0]
> +
> +       ldr     r0, =0x10000000         @CHIP_ID_BASE
> +       ldr     r1, [r0]
> +       lsr r1, r1, #8
> +       and r1, r1, #3
> +       cmp r1, #2
> +       bne v310
> +
> +       /* CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC */
> +       ldr     r0, =0x10030000         @CMU_BASE
> +       ldr     r1, =0x13113113
> +       ldr     r2, =0x10500            @CLK_DIV_DMC0_OFFSET
> +       str     r1, [r0, r2]
> +
> +#ifdef SET_MIU
> +       ldr     r0, =0x10600000         @MIU_BASE
> +#ifdef CONFIG_MIU_1BIT_INTERLEAVED
> +       ldr     r1, =0x0000000c
> +       str     r1, [r0, #0x400]        @MIU_INTLV_CONFIG
> +       ldr     r1, =0x40000000
> +       str     r1, [r0, #0x808]        @MIU_INTLV_START_ADDR
> +       ldr     r1, =0x5fffffff
> +       str     r1, [r0, #0x810]        @MIU_INTLV_END_ADDR
> +       ldr     r1, =0x00000001
> +       str     r1, [r0, #0x800]        @MIU_MAPPING_UPDATE
> +#endif
> +#ifdef CONFIG_MIU_2BIT_INTERLEAVED
> +       ldr     r1, =0x2000150c
> +       str     r1, [r0, #0x400]        @MIU_INTLV_CONFIG
> +       ldr     r1, =0x40000000
> +       str     r1, [r0, #0x808]        @MIU_INTLV_START_ADDR
> +       ldr     r1, =0x5fffffff
> +       str     r1, [r0, #0x810]        @MIU_INTLV_END_ADDR
> +       ldr     r1, =0x00000001
> +       str     r1, [r0, #0x800]        @MIU_MAPPING_UPDATE
> +#endif
> +#ifdef CONFIG_MIU_LINEAR
> +       ldr     r1, =0x40000000
> +       str     r1, [r0, #0x818]        @MIU_SINGLE_MAPPING0_START_ADDR
> +       ldr     r1, =0x4fffffff
> +       str     r1, [r0, #0x820]        @MIU_SINGLE_MAPPING0_END_ADDR
> +       ldr     r1, =0x50000000
> +       str     r1, [r0, #0x828]        @MIU_SINGLE_MAPPING1_START_ADDR
> +       ldr     r1, =0x5fffffff
> +       str     r1, [r0, #0x830]        @MIU_SINGLE_MAPPING1_END_ADDR]
> +       ldr     r1, =0x00000006
> +       str     r1, [r0, #0x800]        @MIU_MAPPING_UPDATE
> +#endif
> +#endif
> +
> +/*****************************************************************/
> +/*DREX0***********************************************************/
> +/*****************************************************************/

Check the style globally..

> diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
> new file mode 100644
> index 0000000..255ae88
> --- /dev/null
> +++ b/board/samsung/smdkv310/smdkv310.c
> @@ -0,0 +1,138 @@
> +/*
> + * Copyright (C) 2011 Samsung Electronics
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <netdev.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/mmc.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +struct s5pc210_gpio_part1 *gpio1;
> +struct s5pc210_gpio_part2 *gpio2;
> +
> +static void smc9115_pre_init(void)
> +{
> +       unsigned int *ptr;
> +       /* gpio configuration */
> +
> +       writel(0x22222222, 0x11000000 + 0x120);

NAK.
What is 0x11000000 + 0x120?

> +
> +       /* Ethernet needs bus width of 16 bits */
> +       ptr = (unsigned int *) (S5PC210_SROMC_BASE + 0);
> +       *ptr = 0x9999;
> +
> +       /* Select and configure the SROMC bank  (Bank = 1)*/
> +       ptr = (unsigned int *) (S5PC210_SROMC_BASE + 0x08);
> +       *ptr = 0xffffffff;

NAK.
Please use read/write function with structure.

> +}
> +
> +int board_init(void)
> +{
> +       smc9115_pre_init();
> +
> +       gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
> +       gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
> +
> +       gd->bd->bi_arch_number = MACH_TYPE;

Please use MACH_TYPE_SMDKV310 directly.

> +       gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
> +       return 0;
> +}
> +
> +int dram_init(void)
> +{
> +       gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
> +                       + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
> +                       + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
> +                       + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
> +
> +       return 0;
> +}
> +
> +void dram_init_banksize(void)
> +{
> +       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> +       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> +       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
> +       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
> +       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
> +       gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
> +       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
> +       gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +       int rc = 0;
> +#ifdef CONFIG_SMC911X
> +       rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> +#endif
> +       return rc;
> +}
> +
> +#ifdef BOARD_LATE_INIT
> +int board_late_init(void)
> +{
> +       return 0;
> +}
> +#endif

Just return 0?
then, please remove it.
Please don't make dead function.

> +
> +#ifdef CONFIG_DISPLAY_BOARDINFO
> +int checkboard(void)
> +{
> +       unsigned int *ptr = (unsigned int *) S5PC210_PRO_ID;

Please use readl function.

> +       if (((*ptr & 0x300) >> 8) == 2)

Please add some descriptions.

> +               printf("\nBoard: SMDKC210\n");
> +       else
> +               printf("\nBoard: SMDKV310\n");
> +
> +       return 0;
> +}
> +#endif
> +
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 45c3102..8bb245d 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -128,6 +128,7 @@ omap4_sdp4430                arm         armv7       sdp4430             ti
>  s5p_goni                     arm         armv7       goni                samsung        s5pc1xx
>  smdkc100                     arm         armv7       smdkc100            samsung        s5pc1xx
>  s5pc210_universal            arm         armv7       universal_c210      samsung        s5pc2xx
> +smdkv310                    arm         armv7       smdkv310            samsung        s5pc2xx
>  harmony                      arm         armv7       harmony             nvidia         tegra2
>  seaboard                     arm         armv7       seaboard            nvidia         tegra2
>  actux1                       arm         ixp
> diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
> new file mode 100644
> index 0000000..a80f902
> --- /dev/null
> +++ b/include/configs/smdkv310.h
> +/* High Level Configuration Options */
> +#define CONFIG_ARMV7                   1       /*This is an ARM V7 CPU core */
> +#define CONFIG_SAMSUNG                 1       /* in a SAMSUNG core */
> +#define CONFIG_S5P                     1       /* S5P Family */
> +#define CONFIG_S5PC210                 1       /* which is in a S5PC210 SoC */
> +#define CONFIG_SMDKV310                        1       /* working within SMDKV310*/
> +#define CONFIG_EVT1                    1       /* EVT1 */

Is it need?

> +
> +#include <asm/arch/cpu.h>              /* get chip and board defs */
> +
> +#define CONFIG_ARCH_CPU_INIT
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +/* Keep L2 Cache Disabled */
> +#define CONFIG_L2_OFF                  1
> +
> +#define CONFIG_SYS_SDRAM_BASE          0x40000000
> +
> +/* input clock of PLL: SMDKV310 has 24MHz input clock */
> +#define CONFIG_SYS_CLK_FREQ            24000000
> +
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_CMDLINE_EDITING
> +
> +/* Handling Sleep Mode*/
> +#define S5P_CHECK_SLEEP                        0x00000BAD
> +#define S5P_CHECK_DIDLE                        0xBAD00000
> +
> +/* Architecture magic and machine type */
> +#define MACH_TYPE                      2925UL  /* SMDKV310 machine ID */

Please remove it.
Use MACH_TYPE_SMDKV310 define.

> +#define UBOOT_MAGIC                    (0x43090000 | MACH_TYPE)

What is it?

> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (1 << 20))
> +
> +/* size in bytes reserved for initial data */
> +#define CONFIG_SYS_GBL_DATA_SIZE       128

This define doesn't use anywhere.
Please remove it.

> +
> +/* select serial console configuration */
> +#define CONFIG_SERIAL_MULTI            1
> +#define CONFIG_SERIAL1                 1       /* use SERIAL 1 */
> +#define CONFIG_BAUDRATE                        115200
> +#define S5PC210_UART1_OFFSET           0x010000
> +
> +/* SMDKV310 has 4 bank of DRAM */
> +#define CONFIG_NR_DRAM_BANKS   4
> +#define SDRAM_BANK_SIZE                (512 << 20)     /* 512 MB */
> +#define PHYS_SDRAM_1           CONFIG_SYS_SDRAM_BASE
> +#define PHYS_SDRAM_1_SIZE      SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_2           (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
> +#define PHYS_SDRAM_2_SIZE      SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_3           (CONFIG_SYS_SDRAM_BASE + 2 * SDRAM_BANK_SIZE)
> +#define PHYS_SDRAM_3_SIZE      SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_4           (CONFIG_SYS_SDRAM_BASE + 3 * SDRAM_BANK_SIZE)
> +#define PHYS_SDRAM_4_SIZE      SDRAM_BANK_SIZE
> +
remove space.
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH            1
> +#undef CONFIG_CMD_IMLS
> +#define CONFIG_IDENT_STRING            " for SMDKC210/V310"
> +
> +/* base address for uboot */
> +#define CONFIG_SYS_PHY_UBOOT_BASE      (CONFIG_SYS_SDRAM_BASE + 0x3e00000)
> +#define CONFIG_SYS_MMC_UBOOT_START     CONFIG_SYS_PHY_UBOOT_BASE
> +
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ           (4*1024)        /* IRQ stack */
> +#define CONFIG_STACKSIZE_FIQ           (4*1024)        /* FIQ stack */
> +#endif
> +
> +#define CONFIG_CLK_1000_400_200
> +#define CONFIG_BOOTM_LINUX             1

Already defined at config_cmd_default.h
Please remove it.

> +#define CONFIG_INCLUDE_TEST
> +#define CONFIG_IMAGE_BOOT
> +#define USE_MMC2
> +#define MMC_MAX_CHANNEL                        4

What is these defines?

> +
> +#define CONFIG_ENV_IS_IN_MMC           1
> +#define CONFIG_SYS_MMC_ENV_DEV         0
> +#define CONFIG_ENV_SIZE                        (16 << 10)      /* 16 KB */
> +#define RESERVE_BLOCK_SIZE             (512)
> +#define BL1_SIZE                       (16 << 10) /*16 K reserved for BL1*/
> +#define CONFIG_ENV_OFFSET              (RESERVE_BLOCK_SIZE + BL1_SIZE)
> +#define CONFIG_DOS_PARTITION           1
> +
> +#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_LOAD_ADDR - 0x1000000)

#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_LOAD_ADDR -
GENERATED_GBL_DATA_SIZE)
is better.

> +
> +#undef CONFIG_SKIP_RELOCATE_UBOOT
> +#undef CONFIG_USE_NOR_BOOT
> +#undef CONFIG_USE_IRQ
> +#undef CONFIG_NO_SDMMC_DETECTION
> +#undef CONFIG_USB_STORAGE

remove these defines.
Please don't make private defines if you don't have special reason.

Thanks
Minkyu Kang.
Chander Kashyap - April 11, 2011, 10:49 a.m.
Dear Minkyu,

On 1 April 2011 12:52, Minkyu Kang <promsoft@gmail.com> wrote:

> Dear Chander Kashyap,
>
> On 31 March 2011 18:14, Chander Kashyap <chander.kashyap@linaro.org>
> wrote:
> > SMDKV310 board is based on Samsung S5PV310 SOC. This SOC is very much
> > similar to S5PC210.
> >
> > Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
> > Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
> > ---
> >  board/samsung/smdkv310/Makefile        |   46 +++
> >  board/samsung/smdkv310/config.mk       |    1 +
> >  board/samsung/smdkv310/lowlevel_init.S |  549
> +++++++++++++++++++++++++++
> >  board/samsung/smdkv310/mem_setup.S     |  632
> ++++++++++++++++++++++++++++++++
> >  board/samsung/smdkv310/smdkv310.c      |  138 +++++++
> >  boards.cfg                             |    1 +
> >  include/configs/smdkv310.h             |  199 ++++++++++
> >  7 files changed, 1566 insertions(+), 0 deletions(-)
> >  create mode 100644 board/samsung/smdkv310/Makefile
> >  create mode 100644 board/samsung/smdkv310/config.mk
> >  create mode 100644 board/samsung/smdkv310/lowlevel_init.S
> >  create mode 100644 board/samsung/smdkv310/mem_setup.S
> >  create mode 100644 board/samsung/smdkv310/smdkv310.c
> >  create mode 100644 include/configs/smdkv310.h
>
> You missing MAINTAINER entry.
>

I did  not got this. Where to put maintainer entry.


>
> > diff --git a/board/samsung/smdkv310/config.mk b/board/samsung/smdkv310/
> config.mk
> > new file mode 100644
> > index 0000000..19b9e2f
> > --- /dev/null
> > +++ b/board/samsung/smdkv310/config.mk
> > @@ -0,0 +1 @@
> > +CONFIG_SYS_TEXT_BASE = 0x43e00000
>
> Please remove this file.
> And move this define to config file.
>
> > diff --git a/board/samsung/smdkv310/lowlevel_init.S
> b/board/samsung/smdkv310/lowlevel_init.S
> > new file mode 100644
> > index 0000000..ead12b2
> > --- /dev/null
> > +++ b/board/samsung/smdkv310/lowlevel_init.S
> > +#define MEM_DLLl_ON
> > +
>
> please remove this space.
>
Done

>
> > +
> > +_TEXT_BASE:
> > +       .word   CONFIG_SYS_TEXT_BASE
> > +
> > +       .globl lowlevel_init
> > +lowlevel_init:
> > +       push    {lr}
>
> ditto.
>
Done

>
> > +
> > +
> > +       /* r5 has always zero */
> > +       mov     r5, #0
> > +
> > +       ldr     r7, =S5PC210_GPIO_PART1_BASE
> > +       ldr     r6, =S5PC210_GPIO_PART2_BASE
> > +
> > +       /* check reset status  */
> > +       ldr     r0, =(S5PC210_POWER_BASE + 0x81C)       @ INFORM7
> > +        ldr     r1, [r0]
> > +
> > +       /* AFTR wakeup reset */
> > +       ldr     r2, =S5P_CHECK_DIDLE
> > +       cmp     r1, r2
> > +       beq     exit_wakeup
> > +
> > +       /* Sleep wakeup reset */
> > +       ldr     r2, =S5P_CHECK_SLEEP
> > +       cmp     r1, r2
> > +       beq     wakeup_reset
> > +
> > +       /* when we already run in ram, we don't need to relocate U-Boot.
> > +        * and actually, memory controller must be configured before
> U-Boot
> > +        * is running in ram.
> > +        */
>
> We don't allow this comment style.
> Please check it.
>
> http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=Documentation/CodingStyle
>
> > +       ldr     r0, =0x00ffffff         /* r0 <- Mask Bits*/
> > +       bic     r1, pc, r0              /* pc <- current addr of code */
> > +                                       /* r1 <- unmasked bits of pc */
> > +
> > +       ldr     r2, _TEXT_BASE          /* r2 <- original base addr in
> ram */
> > +       bic     r2, r2, r0              /* r2 <- unmasked bits of r2*/
> > +       cmp     r1, r2                  /* compare r1, r2 */
> > +       beq     1f                      /* r0 == r1 then skip sdram init
> */
> > +
> > +       /* init system clock */
> > +       bl system_clock_init
> > +
> > +       /* Memory initialize */
> > +       bl mem_ctrl_asm_init
>
> Is it OK that memory initialize on u-boot?
> Maybe only do on mmc spl?
>
This is generic initialisation Code.  We need this in case of NOR boot. This
initialisation
is excluded in case of SPL boot.

>
> > +
> > +1:
> > +       /* for UART */
> > +       bl uart_asm_init
> > +       bl tzpc_init
> > +       pop     {pc}
> > +
> > +wakeup_reset:
> > +       bl system_clock_init
> > +       bl mem_ctrl_asm_init
> > +       bl tzpc_init
> > +
> > +exit_wakeup:
> > +       /*Load return address and jump to kernel*/
> > +       ldr     r0, =(S5PC210_POWER_BASE + 0x800)       @ INFORM0
> > +
> > +       /* r1 = physical address of s5pc210_cpu_resume function */
> > +       ldr     r1, [r0]
> > +
> > +       /* Jump to kernel*/
> > +       mov     pc, r1
> > +       nop
> > +       nop
> > +
> > +/*
> > + * system_clock_init: Initialize core clock and bus clock.
> > + * void system_clock_init(void)
> > + */
> > +system_clock_init:
> > +       push    {lr}
> > +       ldr     r0, =S5PC210_CLOCK_BASE
> > +
> > +       /* APLL(1), MPLL(1), CORE(0), HPM(0) */
> > +       ldr     r1, =0x0101
> > +       ldr     r2, =0x14200                    @CLK_SRC_CPU
> > +       str     r1, [r0, r2]
> > +
> > +       /* wait ?us */
> > +       mov     r1, #0x10000
> > +1:     subs    r1, r1, #1
> > +       bne     1b
> > +
> > +       ldr     r1, =0x0110
> > +       ldr     r2, =0x0C210                    @CLK_SRC_TOP0
> > +       str     r1, [r0, r2]
> > +
> > +       ldr     r1, =0x00
> > +       ldr     r2, =0x0C214                    @CLK_SRC_TOP1_OFFSET
> > +       str     r1, [r0, r2]
> > +
> > +       /* DMC */
> > +       ldr     r1, =0x00
> > +       ldr     r2, =0x10200                    @CLK_SRC_DMC_OFFSET
> > +       str     r1, [r0, r2]
> > +
> > +       /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
> > +
> > +       ldr     r1, =0x066666
> > +       ldr     r2, =0x0C240                    @ CLK_SRC_FSYS
> > +       str     r1, [r0, r2]
> > +
> > +       /*CLK_SRC_LEFTBUS */
> > +       ldr     r1, =0x00
> > +       ldr     r2, =0x04200                    @CLK_SRC_LEFTBUS_OFFSET
> > +       str     r1, [r0, r2]
> > +
> > +       /*CLK_SRC_RIGHTBUS */
> > +       ldr     r1, =0x00
> > +       ldr     r2, =0x08200                    @CLK_SRC_RIGHTBUS_OFFSET
> > +       str     r1, [r0, r2]
> > +
> > +       /* UART[0:4], PWM: SCLKMPLL(6) */
> > +       ldr     r1, =0x06666666
> > +       ldr     r2, =0x0C250                    @CLK_SRC_PERIL0_OFFSET
> > +       str     r1, [r0, r2]
> > +
> > +       /* wait ?us */
> > +       mov     r1, #0x10000
> > +4:     subs    r1, r1, #1
> > +       bne     4b
> > +
> > +       /* CLK_DIV_CPU0:
> > +               PCLK_DBG_RATIO[20]      0x1
> > +               ATB_RATIO[16]           0x3
> > +               PERIPH_RATIO[12]        0x3
> > +               COREM1_RATIO[8]         0x7
> > +               COREM0_RATIO[4]         0x3
> > +       */
>
> Check the style.
>
> > +       ldr     r1, =0x0133730
> > +       ldr     r2, =0x14500                    @CLK_DIV_CPU0_OFFSET
> > +       str     r1, [r0, r2]
> > +
> > +       /*      CLK_DIV_CPU1
> > +               COPY_RATIO [0]          0x3
> > +       */
>
> ditto.
>
> > diff --git a/board/samsung/smdkv310/mem_setup.S
> b/board/samsung/smdkv310/mem_setup.S
> > new file mode 100644
> > index 0000000..3ff486c
> > --- /dev/null
> > +++ b/board/samsung/smdkv310/mem_setup.S
> > @@ -0,0 +1,632 @@
> > +/*
> > + * Memory setup for SMDKV310 board based on S5PC210
> > + *
> > + * Copyright (C) 2011 Samsung Electronics
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <config.h>
> > +
> > +#define SET_MIU
> > +
> > +#define MEM_DLL
> > +
> > +#ifdef CONFIG_CLK_800_330_165
> > +#define DRAM_CLK_330
> > +#endif
> > +#ifdef CONFIG_CLK_1000_200_200
> > +#define DRAM_CLK_200
> > +#endif
> > +#ifdef CONFIG_CLK_1000_330_165
> > +#define DRAM_CLK_330
> > +#endif
> > +#ifdef CONFIG_CLK_1000_400_200
> > +#define DRAM_CLK_400
> > +#endif
> > +
> > +       .globl mem_ctrl_asm_init
> > +mem_ctrl_asm_init:
> > +
> > +       /* Async bridge configuration at CPU_core */
> > +       /* 1: half_sync */
> > +       /* 0: full_sync */
> > +       ldr r0, =0x10010350
> > +       mov r1, #1
> > +       str r1, [r0]
> > +
> > +       ldr     r0, =0x10000000         @CHIP_ID_BASE
> > +       ldr     r1, [r0]
> > +       lsr r1, r1, #8
> > +       and r1, r1, #3
> > +       cmp r1, #2
> > +       bne v310
> > +
> > +       /* CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC */
> > +       ldr     r0, =0x10030000         @CMU_BASE
> > +       ldr     r1, =0x13113113
> > +       ldr     r2, =0x10500            @CLK_DIV_DMC0_OFFSET
> > +       str     r1, [r0, r2]
> > +
> > +#ifdef SET_MIU
> > +       ldr     r0, =0x10600000         @MIU_BASE
> > +#ifdef CONFIG_MIU_1BIT_INTERLEAVED
> > +       ldr     r1, =0x0000000c
> > +       str     r1, [r0, #0x400]        @MIU_INTLV_CONFIG
> > +       ldr     r1, =0x40000000
> > +       str     r1, [r0, #0x808]        @MIU_INTLV_START_ADDR
> > +       ldr     r1, =0x5fffffff
> > +       str     r1, [r0, #0x810]        @MIU_INTLV_END_ADDR
> > +       ldr     r1, =0x00000001
> > +       str     r1, [r0, #0x800]        @MIU_MAPPING_UPDATE
> > +#endif
> > +#ifdef CONFIG_MIU_2BIT_INTERLEAVED
> > +       ldr     r1, =0x2000150c
> > +       str     r1, [r0, #0x400]        @MIU_INTLV_CONFIG
> > +       ldr     r1, =0x40000000
> > +       str     r1, [r0, #0x808]        @MIU_INTLV_START_ADDR
> > +       ldr     r1, =0x5fffffff
> > +       str     r1, [r0, #0x810]        @MIU_INTLV_END_ADDR
> > +       ldr     r1, =0x00000001
> > +       str     r1, [r0, #0x800]        @MIU_MAPPING_UPDATE
> > +#endif
> > +#ifdef CONFIG_MIU_LINEAR
> > +       ldr     r1, =0x40000000
> > +       str     r1, [r0, #0x818]        @MIU_SINGLE_MAPPING0_START_ADDR
> > +       ldr     r1, =0x4fffffff
> > +       str     r1, [r0, #0x820]        @MIU_SINGLE_MAPPING0_END_ADDR
> > +       ldr     r1, =0x50000000
> > +       str     r1, [r0, #0x828]        @MIU_SINGLE_MAPPING1_START_ADDR
> > +       ldr     r1, =0x5fffffff
> > +       str     r1, [r0, #0x830]        @MIU_SINGLE_MAPPING1_END_ADDR]
> > +       ldr     r1, =0x00000006
> > +       str     r1, [r0, #0x800]        @MIU_MAPPING_UPDATE
> > +#endif
> > +#endif
> > +
> > +/*****************************************************************/
> > +/*DREX0***********************************************************/
> > +/*****************************************************************/
>
> Check the style globally..
>
> > diff --git a/board/samsung/smdkv310/smdkv310.c
> b/board/samsung/smdkv310/smdkv310.c
> > new file mode 100644
> > index 0000000..255ae88
> > --- /dev/null
> > +++ b/board/samsung/smdkv310/smdkv310.c
> > @@ -0,0 +1,138 @@
> > +/*
> > + * Copyright (C) 2011 Samsung Electronics
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <netdev.h>
> > +#include <asm/arch/cpu.h>
> > +#include <asm/arch/gpio.h>
> > +#include <asm/arch/mmc.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +struct s5pc210_gpio_part1 *gpio1;
> > +struct s5pc210_gpio_part2 *gpio2;
> > +
> > +static void smc9115_pre_init(void)
> > +{
> > +       unsigned int *ptr;
> > +       /* gpio configuration */
> > +
> > +       writel(0x22222222, 0x11000000 + 0x120);
>
> NAK.
> What is 0x11000000 + 0x120?
>
Done

>
> > +
> > +       /* Ethernet needs bus width of 16 bits */
> > +       ptr = (unsigned int *) (S5PC210_SROMC_BASE + 0);
> > +       *ptr = 0x9999;
> > +
> > +       /* Select and configure the SROMC bank  (Bank = 1)*/
> > +       ptr = (unsigned int *) (S5PC210_SROMC_BASE + 0x08);
> > +       *ptr = 0xffffffff;
>
> NAK.
> Please use read/write function with structure.
>
Done

>
> > +}
> > +
> > +int board_init(void)
> > +{
> > +       smc9115_pre_init();
> > +
> > +       gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
> > +       gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
> > +
> > +       gd->bd->bi_arch_number = MACH_TYPE;
>
> Please use MACH_TYPE_SMDKV310 directly.
>
> > +       gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
> > +       return 0;
> > +}
> > +
> > +int dram_init(void)
> > +{
> > +       gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1,
> PHYS_SDRAM_1_SIZE)
> > +                       + get_ram_size((long *)PHYS_SDRAM_2,
> PHYS_SDRAM_2_SIZE)
> > +                       + get_ram_size((long *)PHYS_SDRAM_3,
> PHYS_SDRAM_3_SIZE)
> > +                       + get_ram_size((long *)PHYS_SDRAM_4,
> PHYS_SDRAM_4_SIZE);
> > +
> > +       return 0;
> > +}
> > +
> > +void dram_init_banksize(void)
> > +{
> > +       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> > +       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> > +       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
> > +       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
> > +       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
> > +       gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
> > +       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
> > +       gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
> > +}
> > +
> > +int board_eth_init(bd_t *bis)
> > +{
> > +       int rc = 0;
> > +#ifdef CONFIG_SMC911X
> > +       rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> > +#endif
> > +       return rc;
> > +}
> > +
> > +#ifdef BOARD_LATE_INIT
> > +int board_late_init(void)
> > +{
> > +       return 0;
> > +}
> > +#endif
>
> Just return 0?
> then, please remove it.
> Please don't make dead function.
>
> > +
> > +#ifdef CONFIG_DISPLAY_BOARDINFO
> > +int checkboard(void)
> > +{
> > +       unsigned int *ptr = (unsigned int *) S5PC210_PRO_ID;
>
> Please use readl function.
>
> > +       if (((*ptr & 0x300) >> 8) == 2)
>
> Please add some descriptions.
>
> > +               printf("\nBoard: SMDKC210\n");
> > +       else
> > +               printf("\nBoard: SMDKV310\n");
> > +
> > +       return 0;
> > +}
> > +#endif
> > +
> > +#endif
> > diff --git a/boards.cfg b/boards.cfg
> > index 45c3102..8bb245d 100644
> > --- a/boards.cfg
> > +++ b/boards.cfg
> > @@ -128,6 +128,7 @@ omap4_sdp4430                arm         armv7
> sdp4430             ti
> >  s5p_goni                     arm         armv7       goni
>  samsung        s5pc1xx
> >  smdkc100                     arm         armv7       smdkc100
>  samsung        s5pc1xx
> >  s5pc210_universal            arm         armv7       universal_c210
>  samsung        s5pc2xx
> > +smdkv310                    arm         armv7       smdkv310
>  samsung        s5pc2xx
> >  harmony                      arm         armv7       harmony
> nvidia         tegra2
> >  seaboard                     arm         armv7       seaboard
>  nvidia         tegra2
> >  actux1                       arm         ixp
> > diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
> > new file mode 100644
> > index 0000000..a80f902
> > --- /dev/null
> > +++ b/include/configs/smdkv310.h
> > +/* High Level Configuration Options */
> > +#define CONFIG_ARMV7                   1       /*This is an ARM V7 CPU
> core */
> > +#define CONFIG_SAMSUNG                 1       /* in a SAMSUNG core */
> > +#define CONFIG_S5P                     1       /* S5P Family */
> > +#define CONFIG_S5PC210                 1       /* which is in a S5PC210
> SoC */
> > +#define CONFIG_SMDKV310                        1       /* working within
> SMDKV310*/
> > +#define CONFIG_EVT1                    1       /* EVT1 */
>
> Is it need?
>
Not required

> > +
> > +#include <asm/arch/cpu.h>              /* get chip and board defs */
> > +
> > +#define CONFIG_ARCH_CPU_INIT
> > +#define CONFIG_DISPLAY_CPUINFO
> > +#define CONFIG_DISPLAY_BOARDINFO
> > +
> > +/* Keep L2 Cache Disabled */
> > +#define CONFIG_L2_OFF                  1
> > +
> > +#define CONFIG_SYS_SDRAM_BASE          0x40000000
> > +
> > +/* input clock of PLL: SMDKV310 has 24MHz input clock */
> > +#define CONFIG_SYS_CLK_FREQ            24000000
> > +
> > +#define CONFIG_SETUP_MEMORY_TAGS
> > +#define CONFIG_CMDLINE_TAG
> > +#define CONFIG_INITRD_TAG
> > +#define CONFIG_CMDLINE_EDITING
> > +
> > +/* Handling Sleep Mode*/
> > +#define S5P_CHECK_SLEEP                        0x00000BAD
> > +#define S5P_CHECK_DIDLE                        0xBAD00000
> > +
> > +/* Architecture magic and machine type */
> > +#define MACH_TYPE                      2925UL  /* SMDKV310 machine ID */
>
> Please remove it.
> Use MACH_TYPE_SMDKV310 define.
>
> > +#define UBOOT_MAGIC                    (0x43090000 | MACH_TYPE)
>
> What is it?
>
Not required

> > +
> > +/* Size of malloc() pool */
> > +#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (1 << 20))
> > +
> > +/* size in bytes reserved for initial data */
> > +#define CONFIG_SYS_GBL_DATA_SIZE       128
>
> This define doesn't use anywhere.
> Please remove it.
>
Ok

> > +
> > +/* select serial console configuration */
> > +#define CONFIG_SERIAL_MULTI            1
> > +#define CONFIG_SERIAL1                 1       /* use SERIAL 1 */
> > +#define CONFIG_BAUDRATE                        115200
> > +#define S5PC210_UART1_OFFSET           0x010000
> > +
> > +/* SMDKV310 has 4 bank of DRAM */
> > +#define CONFIG_NR_DRAM_BANKS   4
> > +#define SDRAM_BANK_SIZE                (512 << 20)     /* 512 MB */
> > +#define PHYS_SDRAM_1           CONFIG_SYS_SDRAM_BASE
> > +#define PHYS_SDRAM_1_SIZE      SDRAM_BANK_SIZE
> > +#define PHYS_SDRAM_2           (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
> > +#define PHYS_SDRAM_2_SIZE      SDRAM_BANK_SIZE
> > +#define PHYS_SDRAM_3           (CONFIG_SYS_SDRAM_BASE + 2 *
> SDRAM_BANK_SIZE)
> > +#define PHYS_SDRAM_3_SIZE      SDRAM_BANK_SIZE
> > +#define PHYS_SDRAM_4           (CONFIG_SYS_SDRAM_BASE + 3 *
> SDRAM_BANK_SIZE)
> > +#define PHYS_SDRAM_4_SIZE      SDRAM_BANK_SIZE
> > +
> remove space.
> > +
> > +/* FLASH and environment organization */
> > +#define CONFIG_SYS_NO_FLASH            1
> > +#undef CONFIG_CMD_IMLS
> > +#define CONFIG_IDENT_STRING            " for SMDKC210/V310"
> > +
> > +/* base address for uboot */
> > +#define CONFIG_SYS_PHY_UBOOT_BASE      (CONFIG_SYS_SDRAM_BASE +
> 0x3e00000)
> > +#define CONFIG_SYS_MMC_UBOOT_START     CONFIG_SYS_PHY_UBOOT_BASE
> > +
> > +#ifdef CONFIG_USE_IRQ
> > +#define CONFIG_STACKSIZE_IRQ           (4*1024)        /* IRQ stack */
> > +#define CONFIG_STACKSIZE_FIQ           (4*1024)        /* FIQ stack */
> > +#endif
> > +
> > +#define CONFIG_CLK_1000_400_200
> > +#define CONFIG_BOOTM_LINUX             1
>
> Already defined at config_cmd_default.h
> Please remove it.
>
> > +#define CONFIG_INCLUDE_TEST
> > +#define CONFIG_IMAGE_BOOT
> > +#define USE_MMC2
> > +#define MMC_MAX_CHANNEL                        4
>
> What is these defines?
>
> > +
> > +#define CONFIG_ENV_IS_IN_MMC           1
> > +#define CONFIG_SYS_MMC_ENV_DEV         0
> > +#define CONFIG_ENV_SIZE                        (16 << 10)      /* 16 KB
> */
> > +#define RESERVE_BLOCK_SIZE             (512)
> > +#define BL1_SIZE                       (16 << 10) /*16 K reserved for
> BL1*/
> > +#define CONFIG_ENV_OFFSET              (RESERVE_BLOCK_SIZE + BL1_SIZE)
> > +#define CONFIG_DOS_PARTITION           1
> > +
> > +#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_LOAD_ADDR -
> 0x1000000)
>
> #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_LOAD_ADDR -
> GENERATED_GBL_DATA_SIZE)
> is better.
>
> > +
> > +#undef CONFIG_SKIP_RELOCATE_UBOOT
> > +#undef CONFIG_USE_NOR_BOOT
> > +#undef CONFIG_USE_IRQ
> > +#undef CONFIG_NO_SDMMC_DETECTION
> > +#undef CONFIG_USB_STORAGE
>
> remove these defines.
> Please don't make private defines if you don't have special reason.
>
> Thanks
> Minkyu Kang.
> --
> from. prom.
> www.promsoft.net
>
Minkyu Kang - April 13, 2011, 1:36 a.m.
Dear Chander Kashyap,

On 11 April 2011 19:49, Chander Kashyap <chander.kashyap@linaro.org> wrote:
>> > SMDKV310 board is based on Samsung S5PV310 SOC. This SOC is very much
>> > similar to S5PC210.
>> >
>> > Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
>> > Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
>> > ---
>> >  board/samsung/smdkv310/Makefile        |   46 +++
>> >  board/samsung/smdkv310/config.mk       |    1 +
>> >  board/samsung/smdkv310/lowlevel_init.S |  549
>> > +++++++++++++++++++++++++++
>> >  board/samsung/smdkv310/mem_setup.S     |  632
>> > ++++++++++++++++++++++++++++++++
>> >  board/samsung/smdkv310/smdkv310.c      |  138 +++++++
>> >  boards.cfg                             |    1 +
>> >  include/configs/smdkv310.h             |  199 ++++++++++
>> >  7 files changed, 1566 insertions(+), 0 deletions(-)
>> >  create mode 100644 board/samsung/smdkv310/Makefile
>> >  create mode 100644 board/samsung/smdkv310/config.mk
>> >  create mode 100644 board/samsung/smdkv310/lowlevel_init.S
>> >  create mode 100644 board/samsung/smdkv310/mem_setup.S
>> >  create mode 100644 board/samsung/smdkv310/smdkv310.c
>> >  create mode 100644 include/configs/smdkv310.h
>>
>> You missing MAINTAINER entry.
>
> I did  not got this. Where to put maintainer entry.
>

Please see MAINTAINERS.

>> > +       /* Memory initialize */
>> > +       bl mem_ctrl_asm_init
>>
>> Is it OK that memory initialize on u-boot?
>> Maybe only do on mmc spl?
>
> This is generic initialisation Code.  We need this in case of NOR boot. This
> initialisation
> is excluded in case of SPL boot.

How about eMMC boot or OneNAND boot?
Maybe DRAM will be initialized twice, and then system will be hang.
I think need to add ifdef condition.

Thanks
Minkyu Kang

Patch

diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile
new file mode 100644
index 0000000..8e9b703
--- /dev/null
+++ b/board/samsung/smdkv310/Makefile
@@ -0,0 +1,46 @@ 
+#
+# Copyright (C) 2011 Samsung Electronics
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	:= mem_setup.o
+SOBJS	+= lowlevel_init.o
+COBJS	+= smdkv310.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/smdkv310/config.mk b/board/samsung/smdkv310/config.mk
new file mode 100644
index 0000000..19b9e2f
--- /dev/null
+++ b/board/samsung/smdkv310/config.mk
@@ -0,0 +1 @@ 
+CONFIG_SYS_TEXT_BASE = 0x43e00000
diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S
new file mode 100644
index 0000000..ead12b2
--- /dev/null
+++ b/board/samsung/smdkv310/lowlevel_init.S
@@ -0,0 +1,549 @@ 
+/*
+ * Lowlevel setup for SMDKV310 board based on S5PC210
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has GPIO part1 base 0x11400000
+ * r6 has GPIO part2 base 0x11000000
+ */
+
+#define MEM_DLLl_ON
+
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+	push	{lr}
+
+
+	/* r5 has always zero */
+	mov	r5, #0
+
+	ldr	r7, =S5PC210_GPIO_PART1_BASE
+	ldr	r6, =S5PC210_GPIO_PART2_BASE
+
+	/* check reset status  */
+	ldr     r0, =(S5PC210_POWER_BASE + 0x81C)	@ INFORM7
+        ldr     r1, [r0]
+
+	/* AFTR wakeup reset */
+	ldr	r2, =S5P_CHECK_DIDLE
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* Sleep wakeup reset */
+	ldr	r2, =S5P_CHECK_SLEEP
+	cmp	r1, r2
+	beq	wakeup_reset
+
+	/* when we already run in ram, we don't need to relocate U-Boot.
+	 * and actually, memory controller must be configured before U-Boot
+	 * is running in ram.
+	 */
+	ldr	r0, =0x00ffffff		/* r0 <- Mask Bits*/
+	bic	r1, pc, r0		/* pc <- current addr of code */
+					/* r1 <- unmasked bits of pc */
+
+	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
+	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
+	cmp     r1, r2                  /* compare r1, r2 */
+	beq     1f			/* r0 == r1 then skip sdram init */
+
+	/* init system clock */
+	bl system_clock_init
+
+	/* Memory initialize */
+	bl mem_ctrl_asm_init
+
+1:
+	/* for UART */
+	bl uart_asm_init
+	bl tzpc_init
+	pop	{pc}
+
+wakeup_reset:
+	bl system_clock_init
+	bl mem_ctrl_asm_init
+	bl tzpc_init
+
+exit_wakeup:
+	/*Load return address and jump to kernel*/
+	ldr     r0, =(S5PC210_POWER_BASE + 0x800)	@ INFORM0
+
+	/* r1 = physical address of s5pc210_cpu_resume function */
+	ldr	r1, [r0]
+
+	/* Jump to kernel*/
+	mov	pc, r1
+	nop
+	nop
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	push	{lr}
+	ldr	r0, =S5PC210_CLOCK_BASE
+
+	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
+	ldr	r1, =0x0101
+	ldr	r2, =0x14200			@CLK_SRC_CPU
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+1:	subs	r1, r1, #1
+	bne	1b
+
+	ldr	r1, =0x0110
+	ldr	r2, =0x0C210			@CLK_SRC_TOP0
+	str	r1, [r0, r2]
+
+	ldr	r1, =0x00
+	ldr	r2, =0x0C214			@CLK_SRC_TOP1_OFFSET
+	str	r1, [r0, r2]
+
+	/* DMC */
+	ldr	r1, =0x00
+	ldr	r2, =0x10200			@CLK_SRC_DMC_OFFSET
+	str	r1, [r0, r2]
+
+	/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
+
+	ldr	r1, =0x066666
+	ldr	r2, =0x0C240			@ CLK_SRC_FSYS
+	str	r1, [r0, r2]
+
+	/*CLK_SRC_LEFTBUS */
+	ldr	r1, =0x00
+	ldr	r2, =0x04200			@CLK_SRC_LEFTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/*CLK_SRC_RIGHTBUS */
+	ldr	r1, =0x00
+	ldr	r2, =0x08200			@CLK_SRC_RIGHTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/* UART[0:4], PWM: SCLKMPLL(6) */
+	ldr	r1, =0x06666666
+	ldr	r2, =0x0C250			@CLK_SRC_PERIL0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+4:	subs	r1, r1, #1
+	bne	4b
+
+	/* CLK_DIV_CPU0:
+		PCLK_DBG_RATIO[20]	0x1
+		ATB_RATIO[16]		0x3
+		PERIPH_RATIO[12]	0x3
+		COREM1_RATIO[8]		0x7
+		COREM0_RATIO[4]		0x3
+	*/
+	ldr	r1, =0x0133730
+	ldr	r2, =0x14500			@CLK_DIV_CPU0_OFFSET
+	str	r1, [r0, r2]
+
+	/*	CLK_DIV_CPU1
+		COPY_RATIO [0]		0x3
+	*/
+	ldr	r1, =0x03
+	ldr	r2, =0x14504			@CLK_DIV_CPU1_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+2:	subs	r1, r1, #1
+	bne	2b
+
+	/* MMC[0:1] */
+	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C544			@ CLK_DIV_FSYS1
+	str	r1, [r0, r2]
+	/* MMC[2:3] */
+	ldr	r1, =0x000f070f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C548			@ CLK_DIV_FSYS2
+	str	r1, [r0, r2]
+	/* MMC4 */
+	ldr	r1, =0x000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C54C			@ CLK_DIV_FSYS3
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_DMC0:
+		CORE_TIMERS_RATIO[28]	0x1
+		COPY2_RATIO[24]		0x3
+		DMCP_RATIO[20]		0x1
+		DMCD_RATIO[16]		0x1
+		DMC_RATIO[12]		0x1
+		DPHY_RATIO[8]		0x1
+		ACP_PCLK_RATIO[4]	0x1
+		ACP_RATIO[0]		0x3
+	*/
+	ldr	r1, =0x13111113
+	ldr	r2, =0x010500			@CLK_DIV_DMC0_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_DMC1:
+		DPM_RATIO[24]		0x1
+		DVSEM_RATIO[16]		0x1
+		PWI_RATIO[8]		0x1
+	*/
+	ldr	r1, =0x01010100
+	ldr	r2, =0x010504			@CLK_DIV_DMC1_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_PERIL0:
+		UART5_RATIO[20]	8
+		UART4_RATIO[16]	8
+		UART3_RATIO[12]	8
+		UART2_RATIO[8]	8
+		UART1_RATIO[4]	8
+		UART0_RATIO[0]	8
+	*/
+	ldr	r1, =0x774777
+	ldr	r2, =0x0C550			@CLK_DIV_PERIL0_OFFSET
+	str	r1, [r0, r2]
+
+	/* SLIMBUS: ???, PWM */
+	ldr	r1, =0x8
+	ldr	r2, =0x0C55C			@ CLK_DIV_PERIL3
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_TOP:
+		ONENAND_RATIO[16]	0x0
+		ACLK_133_RATIO[12]	0x5
+		ACLK_160_RATIO[8]	0x4
+		ACLK_100_RATIO[4]	0x7
+		ACLK_200_RATIO[0]	0x3
+	*/
+	ldr	r1, =0x05473
+	ldr	r2, =0x0C510			@CLK_DIV_TOP_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_LEFRBUS:
+		GPL_RATIO[4]	0x1
+		GDL_RATIO[0]	0x3
+	*/
+	ldr	r1, =0x013
+	ldr	r2, =0x04500			@CLK_DIV_LEFTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_RIGHTBUS:
+		GPR_RATIO[4]	0x1
+		GDR_RATIO[0]	0x3
+	*/
+	ldr	r1, =0x013
+	ldr	r2, =0x08500			@CLK_DIV_RIGHTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/* Set PLL locktime */
+	ldr	r1, =0x01C20
+	ldr	r2, =0x014000			@APLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =0x01C20
+	ldr	r2, =0x014008			@MPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =0x01C20
+	ldr	r2, =0x0C010			@EPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =0x01C20
+	ldr	r2, =0x0C020			@VPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	/* APLL_CON1:
+		APLL_AFC_ENB[31]	0x1
+		APLL_AFC[0]		0xC
+	*/
+	ldr	r1, =0x8000000C
+	ldr	r2, =0x014104			@APLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/*APLL_CON0:
+		APLL_MDIV[16]	0xFA
+		APLL_PDIV[8]	0x6
+		APLL_SDIV[0]	0x1
+	*/
+	ldr	r1, =0x80FA0601
+	ldr	r2, =0x014100			@APLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* MPLL_CON1:
+		MPLL_AFC_ENB[31]	0x0
+		MPLL_AFC[0]		0x1C
+	*/
+	ldr	r1, =0x01C
+	ldr	r2, =0x01410C			@MPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/*MPLL_CON0:
+		MPLL_MDIV[16]	0xC8
+		MPLL_PDIV[8]	0x6
+		MPLL_SDIV[0]	0x1
+	*/
+	ldr	r1, =0x80C80601
+	ldr	r2, =0x014108			@MPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* EPLL */
+	ldr	r1, =0x0
+	ldr	r2, =0x0C114			@EPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	/* EPLL_CON0:
+		EPLL_MDIV[16]	0x30
+		EPLL_PDIV[8]	0x3
+		EPLL_SDIV[0]	0x2
+	*/
+	ldr	r1, =80300302
+	ldr	r2, =0x0C110			@EPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* VPLL_CON1:
+		VPLL_MRR[24]	0x11
+		VPLL_MFR[16]	0x0
+		VPLL_K[0]	0x400
+	*/
+	ldr	r1, =0x11000400
+	ldr	r2, =0x0C124			@VPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	/* VPLL_CON0:
+		VPLL_MDIV[16]	0x35
+		VPLL_PDIV[8]	0x3
+		VPLL_SDIV[0]	0x2
+	*/
+	ldr	r1, =0x80350302
+	ldr	r2, =0x0C120			@VPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x30000
+3:	subs	r1, r1, #1
+	bne	3b
+
+	ldr	r0, =S5PC2XX_ADDR_BASE		@CHIP_ID_BASE
+	ldr	r1, [r0]
+	lsr r1, r1, #8
+	and r1, r1, #3
+	cmp r1, #2
+	bne v310_2
+
+@ ConControl
+#ifdef MEM_DLLl_ON
+	ldr	r0, =S5PC210_DMC0_BASE		@0x10400000
+
+	ldr	r1, =0x7110100A
+	ldr	r2, =0x18			@DMC_PHYCONTROL0
+	str	r1, [r0, r2]
+	ldr	r1, =0x00000084
+	ldr	r2, =0x1C			@DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+	ldr	r1, =0x7110100B
+	ldr	r2, =0x18			@DMC_PHYCONTROL0
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x20000
+8:	subs	r1, r1, #1
+	bne	8b
+
+	ldr	r1, =0x0000008C
+	ldr	r2, =0x1C			@DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+	ldr	r1, =0x00000084
+	ldr	r2, =0x1C			@DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x20000
+9:	subs	r1, r1, #1
+	bne	9b
+
+	ldr	r0, =S5PC210_DMC1_BASE		@0x10410000
+
+	ldr	r1, =0x7110100A
+	ldr	r2, =0x18			@DMC_PHYCONTROL0
+	str	r1, [r0, r2]
+	ldr	r1, =0x00000084
+	ldr	r2, =0x1C			@DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+	ldr	r1, =0x7110100B
+	ldr	r2, =0x18			@DMC_PHYCONTROL0
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x20000
+10:	subs	r1, r1, #1
+	bne	10b
+
+	ldr	r1, =0x0000008C
+	ldr	r2, =0x1C			@DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+	ldr	r1, =0x00000084
+	ldr	r2, =0x1C			@DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+#endif
+
+	ldr	r0, =S5PC210_DMC0_BASE		@0x10400000
+#ifdef CONFIG_CLK_1000_200_200
+	ldr	r1, =0x0FFF30f0
+#else
+	ldr	r1, =0x0FFF30fa
+#endif
+	ldr	r2, =0x00			@DMC_CONCONTROL
+	str	r1, [r0, r2]
+	ldr	r0, =S5PC210_DMC1_BASE		@0x10410000
+#ifdef CONFIG_CLK_1000_200_200
+	ldr	r1, =0x0FFF30f0
+#else
+	ldr	r1, =0x0FFF30fa
+#endif
+	ldr	r2, =0x00			@DMC_CONCONTROL
+	str	r1, [r0, r2]
+
+v310_2:
+	pop	{pc}
+
+/*
+ *	Check clock until stable.
+ */
+
+	/* Check devider change state */
+wait_div_state1:
+	ldr	r1, =(S5PC210_CLOCK_BASE + 0x1004)	@CLK_DIV_STAT1_OFFSET
+        ldr     r2, [r1]
+	tst	r2, #(0x1<<15)
+	bne	wait_div_state1
+	mov	pc, lr
+
+	/* Check source change state */
+wait_mux_state1:
+	ldr	r1, =(S5PC210_CLOCK_BASE + 0x1104)	@CLK_MUX_STAT1_OFFSET
+        ldr     r2, [r1]
+	tst	r2, #(0x1<<31)
+	bne	wait_mux_state1
+	mov	pc, lr
+
+	/* Check source change state */
+wait_mux_state0:
+	ldr	r1, =(S5PC210_CLOCK_BASE + 0x1100)	@CLK_MUX_STAT0_OFFSET
+        ldr     r2, [r1]
+	tst	r2, #(0x4)
+	bne	wait_mux_state0
+	mov	pc, lr
+
+/*
+ * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
+ * void uart_asm_init(void)
+ */
+	.globl uart_asm_init
+uart_asm_init:
+
+	/*
+	 * setup UART0-UART3 GPIOs (part1)
+	 */
+	mov	r0, r7
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x00]			@ S5PC210_GPIO_A0_OFFSET
+	ldr	r1, =0x00222222
+	str	r1, [r0, #0x20]			@ S5PC210_GPIO_A1_OFFSET
+
+	ldr r0, =S5PC210_UART_BASE
+	add r0, r0, #S5PC210_UART1_OFFSET
+
+	ldr r1, =0x3C5
+	str	r1, [r0, #0x4]
+	ldr r1, =0x111
+	str	r1, [r0, #0x8]
+	ldr r1, =0x3
+	str	r1, [r0, #0x0]
+	ldr r1, =0x35
+	str	r1, [r0, #0x28]
+	ldr r1, =0x4
+	str	r1, [r0, #0x2c]
+
+	mov	pc, lr
+	nop
+	nop
+	nop
+
+/*
+ * Setting TZPC[TrustZone Protection Controller]
+ */
+
+tzpc_init:
+	ldr	r0, =0x10110000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10120000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10130000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10140000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10150000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	mov	pc, lr
diff --git a/board/samsung/smdkv310/mem_setup.S b/board/samsung/smdkv310/mem_setup.S
new file mode 100644
index 0000000..3ff486c
--- /dev/null
+++ b/board/samsung/smdkv310/mem_setup.S
@@ -0,0 +1,632 @@ 
+/*
+ * Memory setup for SMDKV310 board based on S5PC210
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#define SET_MIU
+
+#define MEM_DLL
+
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200
+#endif
+#ifdef CONFIG_CLK_1000_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_400_200
+#define DRAM_CLK_400
+#endif
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+
+	/* Async bridge configuration at CPU_core */
+	/* 1: half_sync */
+	/* 0: full_sync */
+	ldr r0, =0x10010350
+	mov r1, #1
+	str r1, [r0]
+
+	ldr	r0, =0x10000000		@CHIP_ID_BASE
+	ldr	r1, [r0]
+	lsr r1, r1, #8
+	and r1, r1, #3
+	cmp r1, #2
+	bne v310
+
+	/* CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC */
+	ldr	r0, =0x10030000		@CMU_BASE
+	ldr	r1, =0x13113113
+	ldr	r2, =0x10500		@CLK_DIV_DMC0_OFFSET
+	str	r1, [r0, r2]
+
+#ifdef SET_MIU
+	ldr	r0, =0x10600000		@MIU_BASE
+#ifdef CONFIG_MIU_1BIT_INTERLEAVED
+	ldr	r1, =0x0000000c
+	str	r1, [r0, #0x400]	@MIU_INTLV_CONFIG
+	ldr	r1, =0x40000000
+	str	r1, [r0, #0x808]	@MIU_INTLV_START_ADDR
+	ldr	r1, =0x5fffffff
+	str	r1, [r0, #0x810]	@MIU_INTLV_END_ADDR
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
+#endif
+#ifdef CONFIG_MIU_2BIT_INTERLEAVED
+	ldr	r1, =0x2000150c
+	str	r1, [r0, #0x400]	@MIU_INTLV_CONFIG
+	ldr	r1, =0x40000000
+	str	r1, [r0, #0x808]	@MIU_INTLV_START_ADDR
+	ldr	r1, =0x5fffffff
+	str	r1, [r0, #0x810]	@MIU_INTLV_END_ADDR
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
+#endif
+#ifdef CONFIG_MIU_LINEAR
+	ldr	r1, =0x40000000
+	str	r1, [r0, #0x818]	@MIU_SINGLE_MAPPING0_START_ADDR
+	ldr	r1, =0x4fffffff
+	str	r1, [r0, #0x820]	@MIU_SINGLE_MAPPING0_END_ADDR
+	ldr	r1, =0x50000000
+	str	r1, [r0, #0x828]	@MIU_SINGLE_MAPPING1_START_ADDR
+	ldr	r1, =0x5fffffff
+	str	r1, [r0, #0x830]	@MIU_SINGLE_MAPPING1_END_ADDR]
+	ldr	r1, =0x00000006
+	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
+#endif
+#endif
+
+/*****************************************************************/
+/*DREX0***********************************************************/
+/*****************************************************************/
+	ldr	r0, =0x10400000		@APB_DMC_0_BASE
+
+	ldr	r1, =0xE3855503
+	str	r1, [r0, #0x44]		@DMC_PHYZQCONTROL
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x0000008C
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x0000008C
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x20]		@DMC_PHYCONTROL2
+
+	ldr	r1, =0x0FFF30da
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+	ldr	r1, =0x00202500
+	str	r1, [r0, #0x04]		@DMC_MEMCONTROL]
+#ifdef MIU_LINEAR
+	ldr	r1, =0x40f01223
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+#else	/* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
+	ldr	r1, =0x20f01223
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+#endif
+	ldr	r1, =0xff000000
+	str	r1, [r0, #0x14]		@DMC_PRECHCONFIG
+
+	ldr	r1, =0x0000005D
+	str	r1, [r0, #0x30]		@DMC_TIMINGAREF
+
+#ifdef DRAM_CLK_200
+	ldr	r1, =0x1A254349
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x23230306
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x281c0235
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+#ifdef DRAM_CLK_330
+	ldr	r1, =0x2b47654e
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x35330306
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x442f0365
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+#ifdef DRAM_CLK_400
+	ldr	r1, =0x34498691
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x36330306
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x50380365
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+
+	mov	r2, #0x100000
+2:	subs	r2, r2, #1
+	bne	2b
+	ldr	r1, =0x07000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	mov	r2, #0x100000
+3:	subs	r2, r2, #1
+	bne	3b
+	ldr	r1, =0x00071C00
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	mov	r2, #0x100000
+4:	subs	r2, r2, #1
+	bne	4b
+
+	ldr	r1, =0x00010BFC
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	mov	r2, #0x100000
+5:	subs	r2, r2, #1
+	bne	5b
+	ldr	r1, =0x00000488
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00000810
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00000C08
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+/*****************************************************************/
+/*DREX1***********************************************************/
+/*****************************************************************/
+	ldr	r0, =0x10410000		@APB_DMC_1_BASE
+	ldr	r1, =0xE3855503
+	str	r1, [r0, #0x44]		@DMC_PHYZQCONTROL
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x0000008C
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x0000008C
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x20]		@DMC_PHYCONTROL2
+
+	ldr	r1, =0x0FFF30da
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+	ldr	r1, =0x00202500
+	str	r1, [r0, #0x04]		@DMC_MEMCONTROL]
+#ifdef MIU_LINEAR
+	ldr	r1, =0x40f01223
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+#else	/* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
+	ldr	r1, =0x20f01223
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+#endif
+	ldr	r1, =0xff000000
+	str	r1, [r0, #0x14]		@DMC_PRECHCONFIG
+
+	ldr	r1, =0x0000005D
+	str	r1, [r0, #0x30]		@DMC_TIMINGAREF
+
+#ifdef DRAM_CLK_200
+	ldr	r1, =0x1A254349
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x23230306
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x281c0235
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+#ifdef DRAM_CLK_330
+	ldr	r1, =0x2b47654e
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x35330306
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x442f0365
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+#ifdef DRAM_CLK_400
+	ldr	r1, =0x34498691
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x36330306
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x50380365
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+
+	mov	r2, #0x100000
+2:	subs	r2, r2, #1
+	bne	2b
+	ldr	r1, =0x07000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	mov	r2, #0x100000
+3:	subs	r2, r2, #1
+	bne	3b
+	ldr	r1, =0x00071C00
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	mov	r2, #0x100000
+4:	subs	r2, r2, #1
+	bne	4b
+
+	ldr	r1, =0x00010BFC
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	mov	r2, #0x100000
+5:	subs	r2, r2, #1
+	bne	5b
+	ldr	r1, =0x00000488
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00000810
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00000C08
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	pc, lr
+
+v310:
+
+#ifdef SET_MIU
+	ldr	r0, =0x10600000		@MIU_BASE
+#ifdef CONFIG_MIU_1BIT_INTERLEAVED
+	ldr	r1, =0x0000000c
+	str	r1, [r0, #0x400]	@MIU_INTLV_CONFIG
+	ldr	r1, =0x40000000
+	str	r1, [r0, #0x808]	@MIU_INTLV_START_ADDR
+	ldr	r1, =0xbfffffff
+	str	r1, [r0, #0x810]	@MIU_INTLV_END_ADDR
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
+#endif
+#ifdef CONFIG_MIU_2BIT_INTERLEAVED
+	ldr	r1, =0x2000150c
+	str	r1, [r0, #0x400]	@MIU_INTLV_CONFIG
+	ldr	r1, =0x40000000
+	str	r1, [r0, #0x808]	@MIU_INTLV_START_ADDR
+	ldr	r1, =0xbfffffff
+	str	r1, [r0, #0x810]	@MIU_INTLV_END_ADDR
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
+#endif
+#ifdef CONFIG_MIU_LINEAR
+	ldr	r1, =0x40000000
+	str	r1, [r0, #0x818]	@MIU_SINGLE_MAPPING0_START_ADDR
+	ldr	r1, =0x7fffffff
+	str	r1, [r0, #0x820]	@MIU_SINGLE_MAPPING0_END_ADDR
+	ldr	r1, =0x80000000
+	str	r1, [r0, #0x828]	@MIU_SINGLE_MAPPING1_START_ADDR
+	ldr	r1, =0xbfffffff
+	str	r1, [r0, #0x830]	@MIU_SINGLE_MAPPING1_END_ADDR]
+	ldr	r1, =0x00000006
+	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
+#endif
+#endif
+
+/*****************************************************************/
+/*DREX0***********************************************************/
+/*****************************************************************/
+
+	ldr	r0, =0x10400000		@APB_DMC_0_BASE
+
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0xE3855703
+	str	r1, [r0, #0x44]		@DMC_PHYZQCONTROL
+
+	mov	r2, #0x100000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0x7110100B
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x20]		@DMC_PHYCONTROL2
+
+	ldr	r1, =0x0FFF301a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+	ldr	r1, =0x00312640
+	str	r1, [r0, #0x04]		@DMC_MEMCONTROL]
+
+#ifdef MIU_LINEAR
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x60e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#else	/* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
+	ldr	r1, =0x20e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#endif
+
+	ldr	r1, =0xff000000
+	str	r1, [r0, #0x14]		@DMC_PRECHCONFIG
+
+	ldr	r1, =0x000000BC
+	str	r1, [r0, #0x30]		@DMC_TIMINGAREF
+
+#ifdef DRAM_CLK_330
+	ldr	r1, =0x3545548d
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x45430506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x4439033c
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+#ifdef DRAM_CLK_400
+	ldr	r1, =0x4046654f
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x56500506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x5444033d
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+
+	ldr	r1, =0x07000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+2:	subs	r2, r2, #1
+	bne	2b
+
+	ldr	r1, =0x00020000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00030000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00010002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00000328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+3:	subs	r2, r2, #1
+	bne	3b
+
+	ldr	r1, =0x0a000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+4:	subs	r2, r2, #1
+	bne	4b
+
+	ldr	r1, =0x07100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+5:	subs	r2, r2, #1
+	bne	5b
+
+	ldr	r1, =0x00120000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00130000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00110002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00100328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+6:	subs	r2, r2, #1
+	bne	6b
+
+	ldr	r1, =0x0a100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+7:	subs	r2, r2, #1
+	bne	7b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	mov	r2, #0x100000
+8:	subs	r2, r2, #1
+	bne	8b
+
+/*****************************************************************/
+/*DREX1***********************************************************/
+/*****************************************************************/
+
+	ldr	r0, =0x10410000		@APB_DMC_1_BASE
+
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0xE3855703
+	str	r1, [r0, #0x44]		@DMC_PHYZQCONTROL
+
+	mov	r2, #0x100000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0x7110100B
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x20]		@DMC_PHYCONTROL2
+
+	ldr	r1, =0x0FFF301a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+	ldr	r1, =0x00312640
+	str	r1, [r0, #0x04]		@DMC_MEMCONTROL]
+
+#ifdef MIU_LINEAR
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x60e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#else	/* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
+	ldr	r1, =0x20e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#endif
+
+	ldr	r1, =0xff000000
+	str	r1, [r0, #0x14]		@DMC_PRECHCONFIG
+
+	ldr	r1, =0x000000BC
+	str	r1, [r0, #0x30]		@DMC_TIMINGAREF
+
+#ifdef DRAM_CLK_330
+	ldr	r1, =0x3545548d
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x45430506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x4439033c
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+#ifdef DRAM_CLK_400
+	ldr	r1, =0x4046654f
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x56500506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x5444033d
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+
+	ldr	r1, =0x07000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+2:	subs	r2, r2, #1
+	bne	2b
+
+	ldr	r1, =0x00020000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00030000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00010002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00000328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+3:	subs	r2, r2, #1
+	bne	3b
+
+	ldr	r1, =0x0a000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+4:	subs	r2, r2, #1
+	bne	4b
+
+	ldr	r1, =0x07100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+5:	subs	r2, r2, #1
+	bne	5b
+
+	ldr	r1, =0x00120000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00130000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00110002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00100328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+6:	subs	r2, r2, #1
+	bne	6b
+
+	ldr	r1, =0x0a100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+7:	subs	r2, r2, #1
+	bne	7b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	mov	r2, #0x100000
+8:	subs	r2, r2, #1
+	bne	8b
+
+/*****************************************************************/
+/* turn on DREX0, DREX1 ******************************************/
+/*****************************************************************/
+
+	ldr	r0, =0x10400000		@APB_DMC_0_BASE
+	ldr	r1, =0x0FFF303a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+
+	ldr	r0, =0x10410000		@APB_DMC_1_BASE
+	ldr	r1, =0x0FFF303a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+
+	mov	pc, lr
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
new file mode 100644
index 0000000..255ae88
--- /dev/null
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -0,0 +1,138 @@ 
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+struct s5pc210_gpio_part1 *gpio1;
+struct s5pc210_gpio_part2 *gpio2;
+
+static void smc9115_pre_init(void)
+{
+	unsigned int *ptr;
+	/* gpio configuration */
+
+	writel(0x22222222, 0x11000000 + 0x120);
+
+	/* Ethernet needs bus width of 16 bits */
+	ptr = (unsigned int *) (S5PC210_SROMC_BASE + 0);
+	*ptr = 0x9999;
+
+	/* Select and configure the SROMC bank  (Bank = 1)*/
+	ptr = (unsigned int *) (S5PC210_SROMC_BASE + 0x08);
+	*ptr = 0xffffffff;
+}
+
+int board_init(void)
+{
+	smc9115_pre_init();
+
+	gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
+	gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+
+	gd->bd->bi_arch_number = MACH_TYPE;
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	unsigned int *ptr = (unsigned int *) S5PC210_PRO_ID;
+	if (((*ptr & 0x300) >> 8) == 2)
+		printf("\nBoard: SMDKC210\n");
+	else
+		printf("\nBoard: SMDKV310\n");
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int i, err;
+
+	/*
+	 * MMC2 SD card GPIO:
+	 * GPK2[0]	SD_2_CLK(2)
+	 * GPK2[1]	SD_2_CMD(2)
+	 * GPK2[2]	SD_2_CDn	-> Not used
+	 * GPK2[3:6]	SD_2_DATA[0:3](2)
+	 */
+	for (i = 0; i < 7; i++) {
+		if (i == 2)
+			continue;
+		/* GPK2[0:6] special function 2 */
+		gpio_cfg_pin(&gpio2->k2, i, 0x2);
+		/* GPK2[0:6] pull disable */
+		gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+		/* GPK2[0:6] drv 4x */
+		gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+	}
+	err = s5p_mmc_init(2, 4);
+	return err;
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 45c3102..8bb245d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -128,6 +128,7 @@  omap4_sdp4430                arm         armv7       sdp4430             ti
 s5p_goni                     arm         armv7       goni                samsung        s5pc1xx
 smdkc100                     arm         armv7       smdkc100            samsung        s5pc1xx
 s5pc210_universal            arm         armv7       universal_c210      samsung        s5pc2xx
+smdkv310		     arm         armv7       smdkv310		 samsung        s5pc2xx
 harmony                      arm         armv7       harmony             nvidia         tegra2
 seaboard                     arm         armv7       seaboard            nvidia         tegra2
 actux1                       arm         ixp
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
new file mode 100644
index 0000000..a80f902
--- /dev/null
+++ b/include/configs/smdkv310.h
@@ -0,0 +1,199 @@ 
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG SMDKV310 (S5PC210) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_ARMV7			1	/*This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG			1	/* in a SAMSUNG core */
+#define CONFIG_S5P			1	/* S5P Family */
+#define CONFIG_S5PC210			1	/* which is in a S5PC210 SoC */
+#define CONFIG_SMDKV310			1	/* working within SMDKV310*/
+#define CONFIG_EVT1			1	/* EVT1 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF			1
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+/* input clock of PLL: SMDKV310 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* Handling Sleep Mode*/
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+
+/* Architecture magic and machine type */
+#define MACH_TYPE			2925UL	/* SMDKV310 machine ID */
+#define UBOOT_MAGIC			(0x43090000 | MACH_TYPE)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/* select serial console configuration */
+#define CONFIG_SERIAL_MULTI		1
+#define CONFIG_SERIAL1			1	/* use SERIAL 1 */
+#define CONFIG_BAUDRATE			115200
+#define S5PC210_UART1_OFFSET		0x010000
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_S5P_MMC			1
+
+/* PWM */
+#define CONFIG_PWM			1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_FAT
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_MMC_U_BOOT
+
+#define CONFIG_MTDPARTITION		"80000 400000 3000000"
+#define CONFIG_BOOTCOMMAND		"mmc read 0 40007000 441 2000;\
+					bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"SMDKV310 # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ			1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256KB */
+
+/* SMDKV310 has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS	4
+#define SDRAM_BANK_SIZE		(512 << 20)	/* 512 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + 2 * SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + 3 * SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH		1
+#undef	CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING		" for SMDKC210/V310"
+
+/* base address for uboot */
+#define CONFIG_SYS_PHY_UBOOT_BASE	(CONFIG_SYS_SDRAM_BASE + 0x3e00000)
+#define CONFIG_SYS_MMC_UBOOT_START	CONFIG_SYS_PHY_UBOOT_BASE
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
+#endif
+
+#define CONFIG_CLK_1000_400_200
+#define CONFIG_BOOTM_LINUX		1
+#define CONFIG_INCLUDE_TEST
+#define CONFIG_IMAGE_BOOT
+#define BOARD_LATE_INIT
+
+/* MIU (Memory Interleaving Unit) */
+#define CONFIG_MIU_2BIT_INTERLEAVED
+
+/* The macro for MMC channel 0 is defined by default and can't be undefined */
+#define USE_MMC2
+#define MMC_MAX_CHANNEL			4
+
+#define CONFIG_ENV_IS_IN_MMC		1
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
+#define RESERVE_BLOCK_SIZE		(512)
+#define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
+#define CONFIG_DOS_PARTITION		1
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define	COPY_BL2_SIZE			0x80000
+#define BL2_SIZE_BLOC_COUNT		(COPY_BL2_SIZE/512)
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE		0x5000000
+#define CONFIG_SMC911X_16_BIT
+#endif /*CONFIG_CMD_NET*/
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_NOR_BOOT
+#undef CONFIG_USE_IRQ
+
+/*
+ * SD/MMC detection takes a little long time
+ * So, you can ignore detection process for SD/MMC card
+ */
+#undef	CONFIG_NO_SDMMC_DETECTION
+#undef	CONFIG_USB_STORAGE
+#endif	/* __CONFIG_H */