From patchwork Fri Mar 23 23:45:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 890341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="QOhDR3sv"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="RTmQH6GG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 407KsJ5tMlz9s0n for ; Sat, 24 Mar 2018 10:45:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751657AbeCWXpH (ORCPT ); Fri, 23 Mar 2018 19:45:07 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50778 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751400AbeCWXpF (ORCPT ); Fri, 23 Mar 2018 19:45:05 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6E8E260C66; Fri, 23 Mar 2018 23:45:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521848705; bh=iY5aK9ihlyU2gfoe+PV/yjoc/NJUkbMhcbRpsYKMMbI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QOhDR3svA7FCFzzUCuTdDenwcSWkIB2zQYYC2/vdxqsVN8YsTYwsM2bZvOYKRe7HB Dn8L2U96K4vdLbudJhNimskw1e7fpZoz+CBeoCp5wM9nfXELlQ2YIyp6jIIVaonch/ 1fnEcyvfXF/y4i2ij9cJiOUPXqMB9HSg/qkk6oOs= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from timur-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: timur@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C95D960271; Fri, 23 Mar 2018 23:45:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521848704; bh=iY5aK9ihlyU2gfoe+PV/yjoc/NJUkbMhcbRpsYKMMbI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RTmQH6GGf2ELfQv1QK8DVfFaaA/9wQMbiEkn2FUeS/OksICf9M/ye7bPapGXXNzXU c3pVCRj7I9FGKvidZRXVx5uEY3MSmNe7XAb4vOcGrtshQxa1Ym3EjZvRVwjshODTf9 P962lUPiJAdvbwzEd+7BiVsqY/Wsg0h2olgbnWHo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C95D960271 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: Bjorn Andersson , Linus Walleij , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org Cc: timur@codeaurora.org Subject: [PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002 Date: Fri, 23 Mar 2018 18:45:00 -0500 Message-Id: <1521848700-22214-2-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521848700-22214-1-git-send-email-timur@codeaurora.org> References: <1521848700-22214-1-git-send-email-timur@codeaurora.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Newer versions of the firmware for the Qualcomm Datacenter Technologies QDF2400 restricts access to a subset of the GPIOs on the TLMM. To prevent older kernels from accidentally accessing the restricted GPIOs, we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002, and introduce a new property "gpios". This property is an array of specific GPIOs that are accessible. When an older kernel boots on newer (restricted) firmware, it will fail to probe. To implement the sparse GPIO map, we register all of the GPIOs, but fill in the data only for available GPIOs. This ensures that the driver cannot accidentally access an unavailable GPIO. The pinctrl-msm driver also scans the "gpios" property to determine which pins are available, and ensure that only those can be registered. Support for QCOM8001 is removed as there is no longer any firmware that implements it. Signed-off-by: Timur Tabi Acked-by: Bjorn Andersson Reviewed-by: Stephen Boyd --- drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 114 +++++++++++++++++++++------------ 1 file changed, 73 insertions(+), 41 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c index bb3ce5c3e18b..1dfbe42dd895 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -30,9 +30,7 @@ #include "pinctrl-msm.h" -static struct msm_pinctrl_soc_data qdf2xxx_pinctrl; - -/* A reasonable limit to the number of GPIOS */ +/* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */ #define MAX_GPIOS 256 /* maximum size of each gpio name (enough room for "gpioXXX" + null) */ @@ -40,77 +38,111 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) { + struct msm_pinctrl_soc_data *pinctrl; struct pinctrl_pin_desc *pins; struct msm_pingroup *groups; char (*names)[NAME_SIZE]; unsigned int i; u32 num_gpios; + unsigned int avail_gpios; /* The number of GPIOs we support */ + u8 gpios[MAX_GPIOS]; /* An array of supported GPIOs */ int ret; /* Query the number of GPIOs from ACPI */ ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios); if (ret < 0) { - dev_warn(&pdev->dev, "missing num-gpios property\n"); + dev_err(&pdev->dev, "missing 'num-gpios' property\n"); return ret; } - if (!num_gpios || num_gpios > MAX_GPIOS) { - dev_warn(&pdev->dev, "invalid num-gpios property\n"); + dev_err(&pdev->dev, "invalid 'num-gpios' property\n"); + return -ENODEV; + } + + /* The number of GPIOs in the approved list */ + ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0); + if (ret < 0) { + dev_err(&pdev->dev, "missing 'gpios' property\n"); + return ret; + } + /* + * The number of available GPIOs should be non-zero, and no + * more than the total number of GPIOS. + */ + if (!ret || ret > num_gpios) { + dev_err(&pdev->dev, "invalid 'gpios' property\n"); return -ENODEV; } + avail_gpios = ret; + ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios, + avail_gpios); + if (ret < 0) { + dev_err(&pdev->dev, "could not read list of GPIOs\n"); + return ret; + } + + pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); pins = devm_kcalloc(&pdev->dev, num_gpios, sizeof(struct pinctrl_pin_desc), GFP_KERNEL); groups = devm_kcalloc(&pdev->dev, num_gpios, sizeof(struct msm_pingroup), GFP_KERNEL); - names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL); + names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL); - if (!pins || !groups || !names) + if (!pinctrl || !pins || !groups || !names) return -ENOMEM; + /* + * Initialize the array. GPIOs not listed in the 'gpios' array + * still need a number, but nothing else. + */ for (i = 0; i < num_gpios; i++) { - snprintf(names[i], NAME_SIZE, "gpio%u", i); - pins[i].number = i; - pins[i].name = names[i]; - - groups[i].npins = 1; - groups[i].name = names[i]; groups[i].pins = &pins[i].number; + } - groups[i].ctl_reg = 0x10000 * i; - groups[i].io_reg = 0x04 + 0x10000 * i; - groups[i].intr_cfg_reg = 0x08 + 0x10000 * i; - groups[i].intr_status_reg = 0x0c + 0x10000 * i; - groups[i].intr_target_reg = 0x08 + 0x10000 * i; - - groups[i].mux_bit = 2; - groups[i].pull_bit = 0; - groups[i].drv_bit = 6; - groups[i].oe_bit = 9; - groups[i].in_bit = 0; - groups[i].out_bit = 1; - groups[i].intr_enable_bit = 0; - groups[i].intr_status_bit = 0; - groups[i].intr_target_bit = 5; - groups[i].intr_target_kpss_val = 1; - groups[i].intr_raw_status_bit = 4; - groups[i].intr_polarity_bit = 1; - groups[i].intr_detection_bit = 2; - groups[i].intr_detection_width = 2; + /* Populate the entries that are meant to be exposed as GPIOs. */ + for (i = 0; i < avail_gpios; i++) { + unsigned int gpio = gpios[i]; + + groups[gpio].npins = 1; + snprintf(names[i], NAME_SIZE, "gpio%u", gpio); + pins[gpio].name = names[i]; + groups[gpio].name = names[i]; + + groups[gpio].ctl_reg = 0x10000 * gpio; + groups[gpio].io_reg = 0x04 + 0x10000 * gpio; + groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio; + groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio; + groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio; + + groups[gpio].mux_bit = 2; + groups[gpio].pull_bit = 0; + groups[gpio].drv_bit = 6; + groups[gpio].oe_bit = 9; + groups[gpio].in_bit = 0; + groups[gpio].out_bit = 1; + groups[gpio].intr_enable_bit = 0; + groups[gpio].intr_status_bit = 0; + groups[gpio].intr_target_bit = 5; + groups[gpio].intr_target_kpss_val = 1; + groups[gpio].intr_raw_status_bit = 4; + groups[gpio].intr_polarity_bit = 1; + groups[gpio].intr_detection_bit = 2; + groups[gpio].intr_detection_width = 2; } - qdf2xxx_pinctrl.pins = pins; - qdf2xxx_pinctrl.groups = groups; - qdf2xxx_pinctrl.npins = num_gpios; - qdf2xxx_pinctrl.ngroups = num_gpios; - qdf2xxx_pinctrl.ngpios = num_gpios; + pinctrl->pins = pins; + pinctrl->groups = groups; + pinctrl->npins = num_gpios; + pinctrl->ngroups = num_gpios; + pinctrl->ngpios = num_gpios; - return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl); + return msm_pinctrl_probe(pdev, pinctrl); } static const struct acpi_device_id qdf2xxx_acpi_ids[] = { - {"QCOM8001"}, + {"QCOM8002"}, {}, }; MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);