From patchwork Fri Mar 23 16:34:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 890054 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="IX18golY"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4078Lb716Nz9s0v for ; Sat, 24 Mar 2018 03:36:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752324AbeCWQe7 (ORCPT ); Fri, 23 Mar 2018 12:34:59 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:45541 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751923AbeCWQe5 (ORCPT ); Fri, 23 Mar 2018 12:34:57 -0400 Received: by mail-pg0-f68.google.com with SMTP id y63so1635198pgy.12 for ; Fri, 23 Mar 2018 09:34:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IsEWvgJNcKsjkd8SgDGPMM8oASotOa0bRX2Uz5aPRz4=; b=IX18golYYwxoybZBqWn+4BmYlWXFwOSjf4yV7/E4+OlUJjx4JpIjT5dVYDJjvNOQqu oAUelX4VgJ2EWOq9Zgphlv/CdE6rqVvF5Jewga5jpXVbl3VxQ9/8W/jXC/yDrgEypLrL Ya34ldg6j76OYNGASoBiXdw3Tq8Umozam2fGk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IsEWvgJNcKsjkd8SgDGPMM8oASotOa0bRX2Uz5aPRz4=; b=JoQ6k/t9u8dvAbLSU9AE4Dq5Q1F/axwfXu/4MB+eDGljsJ/HdjMmT/x6Y8T2eFT72t Ht/KoQ95TqALTUHegp4BASk2Cz1kUFQL3Koq8bEcpL1vbOeyxxkltCoR0vmOPPJ+2LOO g2vKdQofTGMnd0bLDhYN94TZfuChZJUmG6D5wTHv1t/rMBKnXA63wGukP8RoDmI1IM2z U3YpcHn9MA5A3TzNEa6onRdiJ55PT6dgqBHU99+QdzGZ5tAtzLLujEdpNI4ZqGPb+H/W IgdiPQpvgPp4f1+/yqiZb+wwfzcQUSwwYmmr1UQlYjFW85JdaINoqsfMxU7qriIFGhAI plfw== X-Gm-Message-State: AElRT7F59+H9hLPSw6sW8Wxr8Ww8v9IP5HvvPeGMZHTi5Q9T/5jW4OmS T4vODo/JFuu75Ta4vpAuIqjqyg== X-Google-Smtp-Source: AG47ELs2UXdPd98Z9Mgxkyjerrplp698cKmP+M/g+F0CbCNntEqvZhXM4vFzKSQQ2uJ16TvEy81BbA== X-Received: by 10.99.96.19 with SMTP id u19mr20948540pgb.261.1521822896786; Fri, 23 Mar 2018 09:34:56 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id s78sm19131294pfa.161.2018.03.23.09.34.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Mar 2018 09:34:56 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Timur Tabi , Bjorn Andersson , Grant Likely , linux-gpio@vger.kernel.org, Andy Shevchenko Subject: [PATCH v4 1/5] dt-bindings: gpio: Add a gpio-reserved-ranges property Date: Fri, 23 Mar 2018 09:34:49 -0700 Message-Id: <20180323163453.96495-2-swboyd@chromium.org> X-Mailer: git-send-email 2.17.0.rc0.231.g781580f067-goog In-Reply-To: <20180323163453.96495-1-swboyd@chromium.org> References: <20180323163453.96495-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Stephen Boyd Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Introduce a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. Cc: Grant Likely Cc: Signed-off-by: Stephen Boyd Signed-off-by: Stephen Boyd Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/gpio/gpio.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index b5de08e3b1a2..a7c31de29362 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -151,9 +151,9 @@ in a lot of designs, some using all 32 bits, some using 18 and some using first 18 GPIOs, at local offset 0 .. 17, are in use. If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an -additional bitmask is needed to specify which GPIOs are actually in use, -and which are dummies. The bindings for this case has not yet been -specified, but should be specified if/when such hardware appears. +additional set of tuples is needed to specify which GPIOs are unusable, with +the gpio-reserved-ranges binding. This property indicates the start and size +of the GPIOs that can't be used. Optionally, a GPIO controller may have a "gpio-line-names" property. This is an array of strings defining the names of the GPIO lines going out of the @@ -178,6 +178,7 @@ gpio-controller@00000000 { gpio-controller; #gpio-cells = <2>; ngpios = <18>; + gpio-reserved-ranges = <0 4>, <12 2>; gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R", "LED G", "LED B", "Col A", "Col B", "Col C", "Col D", "Row A", "Row B", "Row C", "Row D", "NMI button",