[RFC,5/5] devicetree: Add devicetree bindings documentation for

Message ID 1521807722-21626-6-git-send-email-nagasure@xilinx.com
State New
Delegated to: Cyrille Pitchen
Headers show
Series
  • RFC for Zynq QSPI
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Commit Message

Naga Sureshkumar Relli March 23, 2018, 12:22 p.m.
Add bindings documentation for Zynq QSPI driver.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
---
 .../devicetree/bindings/spi/spi-zynq-qspi.txt      | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt

Comments

Miquel Raynal March 23, 2018, 2:47 p.m. | #1
Hi Naga,

On Fri, 23 Mar 2018 17:52:02 +0530, Naga Sureshkumar Relli
<naga.sureshkumar.relli@xilinx.com> wrote:

> Add bindings documentation for Zynq QSPI driver.
> 
> Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
> ---
>  .../devicetree/bindings/spi/spi-zynq-qspi.txt      | 28 ++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> new file mode 100644
> index 0000000..fe3b8e9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
> @@ -0,0 +1,28 @@
> +Xilinx Zynq QSPI controller Device Tree Bindings
> +-------------------------------------------------
> +
> +Required properties:
> +- compatible		: Should be "xlnx,zynq-qspi-1.0".

What is this trailing "-1.0" for?

> +- reg			: Physical base address and size of QSPI registers map.
> +- interrupts		: Property with a value describing the interrupt
> +			  number.
> +- interrupt-parent	: Must be core interrupt controller
> +- clock-names		: List of input clock names - "ref_clk", "pclk"
> +			  (See clock bindings for details).
> +- clocks		: Clock phandles (see clock bindings for details).
> +
> +Optional properties:
> +- num-cs		: Number of chip selects used.
> +- is-dual		: QSPI operating in Dual parallel.
> +- is-satcked		: QSPI operating in Stacked mode.

        ^ stacked

BTW, if you have both is-dual and is-stacked properties in the DT, do
you really need a configuration option for that?

> +
> +Example:
> +	qspi@e000d000 {
> +		compatible = "xlnx,zynq-qspi-1.0";
> +		clock-names = "ref_clk", "pclk";
> +		clocks = <&clkc 10>, <&clkc 43>;
> +		interrupt-parent = <&intc>;
> +		interrupts = <0 19 4>;
> +		num-cs = <1>;
> +		reg = <0xe000d000 0x1000>;
> +	} ;

Thanks,
Miquèl

Patch

diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
new file mode 100644
index 0000000..fe3b8e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
@@ -0,0 +1,28 @@ 
+Xilinx Zynq QSPI controller Device Tree Bindings
+-------------------------------------------------
+
+Required properties:
+- compatible		: Should be "xlnx,zynq-qspi-1.0".
+- reg			: Physical base address and size of QSPI registers map.
+- interrupts		: Property with a value describing the interrupt
+			  number.
+- interrupt-parent	: Must be core interrupt controller
+- clock-names		: List of input clock names - "ref_clk", "pclk"
+			  (See clock bindings for details).
+- clocks		: Clock phandles (see clock bindings for details).
+
+Optional properties:
+- num-cs		: Number of chip selects used.
+- is-dual		: QSPI operating in Dual parallel.
+- is-satcked		: QSPI operating in Stacked mode.
+
+Example:
+	qspi@e000d000 {
+		compatible = "xlnx,zynq-qspi-1.0";
+		clock-names = "ref_clk", "pclk";
+		clocks = <&clkc 10>, <&clkc 43>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 19 4>;
+		num-cs = <1>;
+		reg = <0xe000d000 0x1000>;
+	} ;