@@ -28,6 +28,7 @@ config M68K
select HAVE_PRIVATE_LIBGCC
select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD
+ select DM_NO_OF
config MICROBLAZE
bool "MicroBlaze architecture"
@@ -244,4 +244,8 @@ config DM_DEV_READ_INLINE
bool
default y if !OF_LIVE
+config DM_NO_OF
+ bool
+ default n
+
endmenu
@@ -6,16 +6,23 @@
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
+ * Support for device model:
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/spi_coldfire.h>
#include <spi.h>
#include <malloc.h>
#include <asm/immap.h>
-struct cf_spi_slave {
+struct coldfire_spi_priv {
+#ifndef CONFIG_DM_SPI
struct spi_slave slave;
+#endif
uint baudrate;
int charbit;
};
@@ -39,12 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_MODE_MOD 0x00200000
#define SPI_DBLRATE 0x00100000
-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
-{
- return container_of(slave, struct cf_spi_slave, slave);
-}
-
-static void cfspi_init(void)
+static void __spi_init(void)
{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
@@ -82,7 +84,123 @@ static void cfspi_init(void)
#endif
}
-static void cfspi_tx(u32 ctrl, u16 data)
+int __spi_set_speed(struct coldfire_spi_priv *cfspi, uint bus, uint mode)
+{
+ /*
+ * bit definition for mode:
+ * bit 31 - 28: Transfer size 3 to 16 bits
+ * 27 - 26: PCS to SCK delay prescaler
+ * 25 - 24: After SCK delay prescaler
+ * 23 - 22: Delay after transfer prescaler
+ * 21 : Allow overwrite for bit 31-22 and bit 20-8
+ * 20 : Double baud rate
+ * 19 - 16: PCS to SCK delay scaler
+ * 15 - 12: After SCK delay scaler
+ * 11 - 8: Delay after transfer scaler
+ * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
+ */
+ volatile dspi_t *dspi = (dspi_t *)MMAP_DSPI;
+ int prescaler[] = { 2, 3, 5, 7 };
+ int scaler[] = {
+ 2, 4, 6, 8,
+ 16, 32, 64, 128,
+ 256, 512, 1024, 2048,
+ 4096, 8192, 16384, 32768
+ };
+ int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
+ int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
+ u32 bus_setup = 0;
+
+ tmp = (prescaler[3] * scaler[15]);
+ /* Maximum and minimum baudrate it can handle */
+ if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
+ (cfspi->baudrate < (gd->bus_clk / tmp))) {
+ printf("Exceed baudrate limitation: Max %d - Min %d\n",
+ (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
+ return -1;
+ }
+
+ /* Activate Double Baud when it exceed 1/4 the bus clk */
+ if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
+ (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
+ bus_setup |= DSPI_CTAR_DBR;
+ dbr = 1;
+ }
+
+ /* Overwrite default value set in platform configuration file */
+ if (mode & SPI_MODE_MOD) {
+ /*
+ * Check to see if it is enabled by default in platform
+ * config, or manual setting passed by mode parameter
+ */
+ if (mode & SPI_DBLRATE) {
+ bus_setup |= DSPI_CTAR_DBR;
+ dbr = 1;
+ }
+ }
+
+ pbrcnt = sizeof(prescaler) / sizeof(int);
+ brcnt = sizeof(scaler) / sizeof(int);
+
+ /* baudrate calculation - to closer value, may not be exact match */
+ for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
+ baud_speed = gd->bus_clk / prescaler[i];
+ for (j = 0; j < brcnt; j++) {
+ tmp = (baud_speed / scaler[j]) * (1 + dbr);
+
+ if (tmp > cfspi->baudrate)
+ diff = tmp - cfspi->baudrate;
+ else
+ diff = cfspi->baudrate - tmp;
+
+ if (diff < bestmatch) {
+ bestmatch = diff;
+ best_i = i;
+ best_j = j;
+ }
+ }
+ }
+ bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
+ dspi->ctar[bus] |= bus_setup;
+
+ return 0;
+}
+
+static int __spi_set_mode(struct coldfire_spi_priv *cfspi, uint bus, uint mode)
+{
+ volatile dspi_t *dspi = (dspi_t *)MMAP_DSPI;
+ u32 bus_setup = 0;
+
+ if (mode & SPI_CPOL)
+ bus_setup |= DSPI_CTAR_CPOL;
+ if (mode & SPI_CPHA)
+ bus_setup |= DSPI_CTAR_CPHA;
+ if (mode & SPI_LSB_FIRST)
+ bus_setup |= DSPI_CTAR_LSBFE;
+
+ /* Overwrite default value set in platform configuration file */
+ if (mode & SPI_MODE_MOD) {
+ if ((mode & 0xF0000000) == 0)
+ bus_setup |=
+ dspi->ctar[bus] & 0x78000000;
+ else
+ bus_setup |= ((mode & 0xF0000000) >> 1);
+
+ bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
+ bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
+ } else {
+ bus_setup |= (dspi->ctar[bus] & 0x78FCFFF0);
+ }
+
+ cfspi->charbit =
+ ((dspi->ctar[bus] & 0x78000000) == 0x78000000) ? 16 : 8;
+
+ dspi->ctar[bus] |= bus_setup;
+
+ return 0;
+}
+
+static void __cfspi_tx(u32 ctrl, u16 data)
{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
@@ -91,7 +209,7 @@ static void cfspi_tx(u32 ctrl, u16 data)
dspi->tfr = (ctrl | data);
}
-static u16 cfspi_rx(void)
+static u16 __cfspi_rx(void)
{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
@@ -100,16 +218,15 @@ static u16 cfspi_rx(void)
return (dspi->rfr & 0xFFFF);
}
-static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
- void *din, ulong flags)
+static int __spi_xfer(struct coldfire_spi_priv *cfspi, uint cs, uint bitlen,
+ const void *dout, void *din, ulong flags)
{
- struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
u8 *spi_rd = NULL, *spi_wr = NULL;
static u32 ctrl = 0;
uint len = bitlen >> 3;
- if (cfslave->charbit == 16) {
+ if (cfspi->charbit == 16) {
bitlen >>= 1;
spi_wr16 = (u16 *) dout;
spi_rd16 = (u16 *) din;
@@ -121,25 +238,25 @@ static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
ctrl |= DSPI_TFR_CONT;
- ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
+ ctrl = (ctrl & 0xFF000000) | ((1 << cs) << 16);
if (len > 1) {
int tmp_len = len - 1;
while (tmp_len--) {
if (dout != NULL) {
- if (cfslave->charbit == 16)
- cfspi_tx(ctrl, *spi_wr16++);
+ if (cfspi->charbit == 16)
+ __cfspi_tx(ctrl, *spi_wr16++);
else
- cfspi_tx(ctrl, *spi_wr++);
- cfspi_rx();
+ __cfspi_tx(ctrl, *spi_wr++);
+ __cfspi_rx();
}
if (din != NULL) {
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- if (cfslave->charbit == 16)
- *spi_rd16++ = cfspi_rx();
+ __cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
+ if (cfspi->charbit == 16)
+ *spi_rd16++ = __cfspi_rx();
else
- *spi_rd++ = cfspi_rx();
+ *spi_rd++ = __cfspi_rx();
}
}
@@ -151,135 +268,60 @@ static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
if (len) {
if (dout != NULL) {
- if (cfslave->charbit == 16)
- cfspi_tx(ctrl, *spi_wr16);
+ if (cfspi->charbit == 16)
+ __cfspi_tx(ctrl, *spi_wr16);
else
- cfspi_tx(ctrl, *spi_wr);
- cfspi_rx();
+ __cfspi_tx(ctrl, *spi_wr);
+ __cfspi_rx();
}
if (din != NULL) {
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- if (cfslave->charbit == 16)
- *spi_rd16 = cfspi_rx();
+ __cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
+ if (cfspi->charbit == 16)
+ *spi_rd16 = __cfspi_rx();
else
- *spi_rd = cfspi_rx();
+ *spi_rd = __cfspi_rx();
}
} else {
/* dummy read */
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- cfspi_rx();
+ __cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
+ __cfspi_rx();
}
return 0;
}
-static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
- uint mode)
-{
- /*
- * bit definition for mode:
- * bit 31 - 28: Transfer size 3 to 16 bits
- * 27 - 26: PCS to SCK delay prescaler
- * 25 - 24: After SCK delay prescaler
- * 23 - 22: Delay after transfer prescaler
- * 21 : Allow overwrite for bit 31-22 and bit 20-8
- * 20 : Double baud rate
- * 19 - 16: PCS to SCK delay scaler
- * 15 - 12: After SCK delay scaler
- * 11 - 8: Delay after transfer scaler
- * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
- */
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- int prescaler[] = { 2, 3, 5, 7 };
- int scaler[] = {
- 2, 4, 6, 8,
- 16, 32, 64, 128,
- 256, 512, 1024, 2048,
- 4096, 8192, 16384, 32768
- };
- int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
- int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
- u32 bus_setup = 0;
-
- tmp = (prescaler[3] * scaler[15]);
- /* Maximum and minimum baudrate it can handle */
- if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
- (cfslave->baudrate < (gd->bus_clk / tmp))) {
- printf("Exceed baudrate limitation: Max %d - Min %d\n",
- (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
- return NULL;
- }
+#ifndef CONFIG_DM_SPI
- /* Activate Double Baud when it exceed 1/4 the bus clk */
- if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
- (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
- bus_setup |= DSPI_CTAR_DBR;
- dbr = 1;
- }
-
- if (mode & SPI_CPOL)
- bus_setup |= DSPI_CTAR_CPOL;
- if (mode & SPI_CPHA)
- bus_setup |= DSPI_CTAR_CPHA;
- if (mode & SPI_LSB_FIRST)
- bus_setup |= DSPI_CTAR_LSBFE;
-
- /* Overwrite default value set in platform configuration file */
- if (mode & SPI_MODE_MOD) {
-
- if ((mode & 0xF0000000) == 0)
- bus_setup |=
- dspi->ctar[cfslave->slave.bus] & 0x78000000;
- else
- bus_setup |= ((mode & 0xF0000000) >> 1);
+static inline struct coldfire_spi_priv *to_coldfire_spi_slave
+ (struct spi_slave *slave)
+{
+ return container_of(slave, struct coldfire_spi_priv, slave);
+}
- /*
- * Check to see if it is enabled by default in platform
- * config, or manual setting passed by mode parameter
- */
- if (mode & SPI_DBLRATE) {
- bus_setup |= DSPI_CTAR_DBR;
- dbr = 1;
- }
- bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
- bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
- } else
- bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct coldfire_spi_priv *cfspi;
- cfslave->charbit =
- ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
- 0x78000000) ? 16 : 8;
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
- pbrcnt = sizeof(prescaler) / sizeof(int);
- brcnt = sizeof(scaler) / sizeof(int);
+ cfspi = spi_alloc_slave(struct coldfire_spi_priv, bus, cs);
+ if (!cfspi)
+ return NULL;
- /* baudrate calculation - to closer value, may not be exact match */
- for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
- baud_speed = gd->bus_clk / prescaler[i];
- for (j = 0; j < brcnt; j++) {
- tmp = (baud_speed / scaler[j]) * (1 + dbr);
+ cfspi->baudrate = max_hz;
- if (tmp > cfslave->baudrate)
- diff = tmp - cfslave->baudrate;
- else
- diff = cfslave->baudrate - tmp;
+ if (__spi_set_speed(cfspi, bus, mode))
+ return NULL;
- if (diff < bestmatch) {
- bestmatch = diff;
- best_i = i;
- best_j = j;
- }
- }
- }
- bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
- dspi->ctar[cfslave->slave.bus] = bus_setup;
+ if (__spi_set_mode(cfspi, bus, mode))
+ return NULL;
- return &cfslave->slave;
+ return &cfspi->slave;
}
-#endif /* CONFIG_CF_DSPI */
-#ifdef CONFIG_CMD_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
@@ -298,32 +340,14 @@ void spi_init_r(void)
void spi_init(void)
{
- cfspi_init();
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct cf_spi_slave *cfslave;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
- if (!cfslave)
- return NULL;
-
- cfslave->baudrate = max_hz;
-
- /* specific setup */
- return cfspi_setup_slave(cfslave, mode);
+ __spi_init();
}
void spi_free_slave(struct spi_slave *slave)
{
- struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+ struct coldfire_spi_priv *cfspi = to_coldfire_spi_slave(slave);
- free(cfslave);
+ free(cfspi);
}
int spi_claim_bus(struct spi_slave *slave)
@@ -339,6 +363,88 @@ void spi_release_bus(struct spi_slave *slave)
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
- return cfspi_xfer(slave, bitlen, dout, din, flags);
+ struct coldfire_spi_priv *cfspi = to_coldfire_spi_slave(slave);
+
+ return __spi_xfer(cfspi, slave->cs, bitlen, dout, din, flags);
}
-#endif /* CONFIG_CMD_SPI */
+
+#else
+
+void spi_init(void)
+{
+ /* arch-related port configuration */
+ __spi_init();
+}
+
+static int coldfire_spi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+
+ return cfspi_claim_bus(bus->seq, plat->cs);
+}
+
+static int coldfire_spi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+
+ cfspi_release_bus(bus->seq, plat->cs);
+
+ return 0;
+}
+
+static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din,
+ unsigned long flags)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+
+ return __spi_xfer(cfspi, plat->cs, bitlen, dout, din, flags);
+}
+
+static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
+{
+ struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+
+ return __spi_set_speed(cfspi, bus->seq, plat->mode);
+}
+
+static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+
+ return __spi_set_mode(cfspi, bus->seq, plat->mode);
+}
+
+static int coldfire_spi_probe(struct udevice *bus)
+{
+ struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+
+ cfspi->baudrate = plat->speed_hz;
+
+ return 0;
+}
+
+static const struct dm_spi_ops coldfire_spi_ops = {
+ .claim_bus = coldfire_spi_claim_bus,
+ .release_bus = coldfire_spi_release_bus,
+ .xfer = coldfire_spi_xfer,
+ .set_speed = coldfire_spi_set_speed,
+ .set_mode = coldfire_spi_set_mode,
+};
+
+U_BOOT_DRIVER(coldfire_spi) = {
+ .name = "spi_coldfire",
+ .id = UCLASS_SPI,
+ .probe = coldfire_spi_probe,
+ .ops = &coldfire_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
+};
+#endif /* CONFIG_DM_SPI */
+#endif /* CONFIG_CF_DSPI */
@@ -107,7 +107,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
}
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if !CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(CONFIG_DM_NO_OF)
static int spi_child_post_bind(struct udevice *dev)
{
struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
@@ -121,7 +121,7 @@ static int spi_child_post_bind(struct udevice *dev)
static int spi_post_probe(struct udevice *bus)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if !CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(CONFIG_DM_NO_OF)
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
@@ -274,7 +274,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
bool created = false;
int ret;
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_PLATDATA) || defined(CONFIG_DM_NO_OF)
ret = uclass_first_device_err(UCLASS_SPI, &bus);
#else
ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus);
@@ -283,6 +283,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
printf("Invalid bus %d (err=%d)\n", busnum, ret);
return ret;
}
+
ret = spi_find_chip_select(bus, cs, &dev);
/*
@@ -321,6 +322,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
}
plat = dev_get_parent_platdata(dev);
+
if (!speed) {
speed = plat->max_hz;
mode = plat->mode;
@@ -427,7 +429,7 @@ UCLASS_DRIVER(spi) = {
.id = UCLASS_SPI,
.name = "spi",
.flags = DM_UC_FLAG_SEQ_ALIAS,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if !CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(CONFIG_DM_NO_OF)
.post_bind = dm_scan_fdt_dev,
#endif
.post_probe = spi_post_probe,
@@ -436,7 +438,7 @@ UCLASS_DRIVER(spi) = {
.per_child_auto_alloc_size = sizeof(struct spi_slave),
.per_child_platdata_auto_alloc_size =
sizeof(struct dm_spi_slave_platdata),
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if !CONFIG_IS_ENABLED(OF_PLATDATA) && !defined(CONFIG_DM_NO_OF)
.child_post_bind = spi_child_post_bind,
#endif
};
new file mode 100644
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __spi_coldfire_h
+#define __spi_coldfire_h
+
+/*
+ * struct coldfire_spi_platdata - information about a coldfire spi module
+ *
+ * @speed_hz: SPI speed
+ */
+struct coldfire_spi_platdata {
+ uint speed_hz;
+ uint mode;
+ uint cs;
+};
+
+#endif /* __spi_coldfire_h */
+
This patch adds DM support to cf_spi.c. To be able to build spi driver with DM support, a new config option has been introdiced (DM_NO_DT) since m68k architecture does not support fdt. Signed-off-by: Angelo Dureghello <angelo@sysam.it> --- arch/Kconfig | 1 + drivers/core/Kconfig | 4 + drivers/spi/cf_spi.c | 408 ++++++++++++++++++++------------ drivers/spi/spi-uclass.c | 12 +- include/dm/platform_data/spi_coldfire.h | 22 ++ 5 files changed, 291 insertions(+), 156 deletions(-) create mode 100644 include/dm/platform_data/spi_coldfire.h