[PULL,12/24] RISC-V: Make some header guards more specific

Message ID	1521665220-3869-13-git-send-email-mjc@sifive.com
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Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Michael Clark <mjc@sifive.com> To: qemu-devel@nongnu.org Date: Wed, 21 Mar 2018 13:46:48 -0700 Message-Id: <1521665220-3869-13-git-send-email-mjc@sifive.com> In-Reply-To: <1521665220-3869-1-git-send-email-mjc@sifive.com> References: <1521665220-3869-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 12/24] RISC-V: Make some header guards more specific Precedence: list Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/24] RISC-V: Make virt create_fdt interface consistent \| expand [PULL,01/24] RISC-V: Make virt create_fdt interface consistent [PULL,02/24] RISC-V: Replace hardcoded constants with enum values [PULL,03/24] RISC-V: Make virt board description match spike [PULL,04/24] RISC-V: Use ROM base address and size from memmap [PULL,05/24] RISC-V: Remove identity_translate from load_elf [PULL,06/24] RISC-V: Mark ROM read-only after copying in code [PULL,07/24] RISC-V: Remove unused class definitions [PULL,08/24] RISC-V: Make sure rom has space for fdt [PULL,09/24] RISC-V: Include intruction hex in disassembly [PULL,10/24] RISC-V: Improve page table walker spec compliance [PULL,11/24] RISC-V: Update E order and I extension order [PULL,12/24] RISC-V: Make some header guards more specific [PULL,13/24] RISC-V: Make virt header comment title consistent [PULL,14/24] RISC-V: Use memory_region_is_ram in pte update [PULL,15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection [PULL,16/24] RISC-V: Hardwire satp to 0 for no-mmu case [PULL,17/24] RISC-V: Remove braces from satp case statement [PULL,18/24] RISC-V: riscv-qemu port supports sv39 and sv48 [PULL,19/24] RISC-V: vectored traps are optional [PULL,20/24] RISC-V: No traps on writes to misa, minstret, mcycle [PULL,21/24] RISC-V: Remove support for adhoc X_COP interrupt [PULL,22/24] RISC-V: Convert cpu definition towards future model [PULL,23/24] RISC-V: Clear mtval/stval on exceptions without info [PULL,24/24] RISC-V: Remove erroneous comment from translate.c

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1521665220-3869-13-git-send-email-mjc@sifive.com

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New

Headers

From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Date: Wed, 21 Mar 2018 13:46:48 -0700
Message-Id: <1521665220-3869-13-git-send-email-mjc@sifive.com>
In-Reply-To: <1521665220-3869-1-git-send-email-mjc@sifive.com>
References: <1521665220-3869-1-git-send-email-mjc@sifive.com>
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Subject: [Qemu-devel] [PULL 12/24] RISC-V: Make some header guards more
	specific
Precedence: list
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

[PULL,01/24] RISC-V: Make virt create_fdt interface consistent | expand

Commit Message

Michael Clark March 21, 2018, 8:46 p.m. UTC

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/riscv/spike.h | 4 ++--
 include/hw/riscv/virt.h  | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index 8410430..641b70d 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -16,8 +16,8 @@ 
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef HW_SPIKE_H
-#define HW_SPIKE_H
+#ifndef HW_RISCV_SPIKE_H
+#define HW_RISCV_SPIKE_H
 
 typedef struct {
     /*< private >*/
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index b91a412..3a4f23e 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -16,8 +16,8 @@ 
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef HW_VIRT_H
-#define HW_VIRT_H
+#ifndef HW_RISCV_VIRT_H
+#define HW_RISCV_VIRT_H
 
 typedef struct {
     /*< private >*/

[PULL,12/24] RISC-V: Make some header guards more specific

Commit Message

Patch