From patchwork Wed Mar 21 16:58:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 888944 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="eUZE7trA"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405wxy1cfwz9s0y for ; Thu, 22 Mar 2018 03:59:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752088AbeCUQ6z (ORCPT ); Wed, 21 Mar 2018 12:58:55 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:35717 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751586AbeCUQ6w (ORCPT ); Wed, 21 Mar 2018 12:58:52 -0400 Received: by mail-pf0-f194.google.com with SMTP id y186so2216822pfb.2 for ; Wed, 21 Mar 2018 09:58:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IsEWvgJNcKsjkd8SgDGPMM8oASotOa0bRX2Uz5aPRz4=; b=eUZE7trArtnpGQ+ass4gltzLJ/Y2c6gKUuqIew50pDpt3ym2qEel822QDk7vVRsD6q SW0LMJ7wnJ+7TUbCN8o/kORcow6QCFrIzv3fSAlw2tX0BpLPVVNfnLuSBHOEURV/Mqhw v5xcLdeh//1xUdmCVyftf9fYcPE+wh6szSIP4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IsEWvgJNcKsjkd8SgDGPMM8oASotOa0bRX2Uz5aPRz4=; b=ViPk8Xra2wrDeRTpyI/Y0vtq29cvIpp7WT91+vBOr/+G7wvFZyODosBtEdXMkc/P2A h+xEE2SzNjD4Si1CdZnfbWrQOaCGR2Ihz0Znu6n73BZoXKMsJfrXuqLfYSIM4xu/xtqI t39OisbdyryaE8y8Y95Q2LT6bJgazQrh0MCdtGdMjaw/68EuN+fI1vW2P/AaKSrWsfJY ytrB5U0hOdJcC/ECZyt7uXYXQvF1HbQ5NWTjrn764Sy+tHQIo9+GN27cB+iB1/LNStA1 kjt2dLMRqkOaKKiNyTILUxw96M6bMwI96+Ydm8Dldk1o1+VSY8HE7mlTPsVdiMWXdCNJ 9DHA== X-Gm-Message-State: AElRT7Epvl9vjnjVROl1OHs2KWY0qLys+WYPs0lssMu3OyysJwe481N2 ZvntqpX0K7NrN3MQMzs9iPPEVQ== X-Google-Smtp-Source: AG47ELtPGd0YthNm11m1F03q7ovnUpUTLpstVC0NBR6S5jRRYr4UnEY2ARJHyFn29bC7fgLOTklYhw== X-Received: by 10.98.37.132 with SMTP id l126mr17746314pfl.102.1521651532265; Wed, 21 Mar 2018 09:58:52 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id u28sm10121806pfl.19.2018.03.21.09.58.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 21 Mar 2018 09:58:51 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Timur Tabi , Bjorn Andersson , Grant Likely , linux-gpio@vger.kernel.org, Andy Shevchenko Subject: [PATCH v3 1/3] dt-bindings: gpio: Add a gpio-reserved-ranges property Date: Wed, 21 Mar 2018 09:58:46 -0700 Message-Id: <20180321165848.89751-2-swboyd@chromium.org> X-Mailer: git-send-email 2.16.2.804.g6dcf76e118-goog In-Reply-To: <20180321165848.89751-1-swboyd@chromium.org> References: <20180321165848.89751-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Stephen Boyd Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Introduce a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. Cc: Grant Likely Cc: Signed-off-by: Stephen Boyd Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/gpio/gpio.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index b5de08e3b1a2..a7c31de29362 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -151,9 +151,9 @@ in a lot of designs, some using all 32 bits, some using 18 and some using first 18 GPIOs, at local offset 0 .. 17, are in use. If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an -additional bitmask is needed to specify which GPIOs are actually in use, -and which are dummies. The bindings for this case has not yet been -specified, but should be specified if/when such hardware appears. +additional set of tuples is needed to specify which GPIOs are unusable, with +the gpio-reserved-ranges binding. This property indicates the start and size +of the GPIOs that can't be used. Optionally, a GPIO controller may have a "gpio-line-names" property. This is an array of strings defining the names of the GPIO lines going out of the @@ -178,6 +178,7 @@ gpio-controller@00000000 { gpio-controller; #gpio-cells = <2>; ngpios = <18>; + gpio-reserved-ranges = <0 4>, <12 2>; gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R", "LED G", "LED B", "Col A", "Col B", "Col C", "Col D", "Row A", "Row B", "Row C", "Row D", "NMI button",