From patchwork Wed Mar 21 04:40:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajkumar Rampelli X-Patchwork-Id: 888555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 405ccl6LkVz9ryk for ; Wed, 21 Mar 2018 15:43:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751794AbeCUEla (ORCPT ); Wed, 21 Mar 2018 00:41:30 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:7465 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751963AbeCUEl1 (ORCPT ); Wed, 21 Mar 2018 00:41:27 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 20 Mar 2018 21:40:11 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 20 Mar 2018 21:41:26 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 20 Mar 2018 21:41:26 -0700 Received: from BGMAIL101.nvidia.com (10.25.59.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:25 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by bgmail101.nvidia.com (10.25.59.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 21 Mar 2018 04:41:21 +0000 Received: from rrajk-ubuntu.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 21 Mar 2018 04:41:12 +0000 From: Rajkumar Rampelli To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 4/9] arm64: tegra: Add Tachometer Controller on Tegra186 Date: Wed, 21 Mar 2018 10:10:39 +0530 Message-ID: <1521607244-29734-5-git-send-email-rrajk@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> References: <1521607244-29734-1-git-send-email-rrajk@nvidia.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The NVIDIA Tegra186 SoC has a Tachometer Controller that analyzes the PWM signal of a Fan and reports the period value through pwm interface. Signed-off-by: Rajkumar Rampelli --- V2: Renamed clock-names/reset-names dt properties values to "tachometer" Renamed compatible property value to "nvidia-tegra186-pwm-tachometer" arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 5 +++++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index bd5305a..13c3e59 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -172,4 +172,9 @@ vin-supply = <&vdd_5v0_sys>; }; }; + + tachometer@39c0000 { + nvidia,pulse-per-rev = <2>; + nvidia,capture-window-len = <2>; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 731cd01..19e1afc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1042,4 +1042,15 @@ reset-names = "pwm"; status = "disabled"; }; + + tegra_tachometer: tachometer@39c0000 { + compatible = "nvidia,tegra186-pwm-tachometer"; + reg = <0x0 0x039c0000 0x0 0x10>; + #pwm-cells = <2>; + clocks = <&bpmp TEGRA186_CLK_TACH>; + clock-names = "tachometer"; + resets = <&bpmp TEGRA186_RESET_TACH>; + reset-names = "tachometer"; + status = "disabled"; + }; };