new file mode 100644
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "imx6ul-u-boot.dtsi"
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ pinctrl_usdhc1: usdhc1grp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ u-boot,dm-spl;
+ };
+};
@@ -87,7 +87,6 @@
};
&usdhc1 {
- u-boot,dm-spl;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -135,7 +134,6 @@
};
pinctrl_usdhc1: usdhc1grp {
- u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
@@ -147,7 +145,6 @@
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
@@ -159,7 +156,6 @@
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
new file mode 100644
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "imx6ul-isiot-u-boot.dtsi"
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ u-boot,dm-spl;
+ };
+};
@@ -50,7 +50,6 @@
};
&usdhc2 {
- u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
@@ -61,7 +60,6 @@
&iomuxc {
pinctrl_usdhc2: usdhc2grp {
- u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
new file mode 100644
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "imx6ul-u-boot.dtsi"
+#include "imx6ul-isiot.dtsi"
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ pinctrl_usdhc1: usdhc1grp {
+ u-boot,dm-spl;
+ };
+};
@@ -82,7 +82,6 @@
};
&usdhc1 {
- u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
@@ -129,7 +128,6 @@
};
pinctrl_usdhc1: usdhc1grp {
- u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ soc {
+ u-boot,dm-spl;
+
+ aips1: aips-bus@02000000 {
+ u-boot,dm-spl;
+
+ gpio1: gpio@0209c000 {
+ u-boot,dm-spl;
+ };
+
+ gpio4: gpio@020a8000 {
+ u-boot,dm-spl;
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ u-boot,dm-spl;
+ };
+ };
+
+ aips2: aips-bus@02100000 {
+ u-boot,dm-spl;
+
+ };
+ };
+};
@@ -134,7 +134,6 @@
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
- u-boot,dm-spl;
pmu {
compatible = "arm,cortex-a7-pmu";
@@ -186,7 +185,6 @@
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
- u-boot,dm-spl;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
@@ -417,7 +415,6 @@
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
<&iomuxc 16 33 16>;
- u-boot,dm-spl;
};
gpio2: gpio@020a0000 {
@@ -454,7 +451,6 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
- u-boot,dm-spl;
};
gpio5: gpio@020ac000 {
@@ -653,7 +649,6 @@
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6ul-iomuxc";
reg = <0x020e0000 0x4000>;
- u-boot,dm-spl;
};
gpr: iomuxc-gpr@020e4000 {
@@ -734,7 +729,6 @@
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
- u-boot,dm-spl;
usbotg1: usb@02184000 {
compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
@@ -8,7 +8,12 @@ F: configs/imx6ul_geam_nand_defconfig
F: configs/imx6ul_isiot_emmc_defconfig
F: configs/imx6ul_isiot_mmc_defconfig
F: configs/imx6ul_isiot_nand_defconfig
+F: arch/arm/dts/imx6ul.dtsi
+F: arch/arm/dts/imx6ul-u-boot.dtsi
F: arch/arm/dts/imx6ul-geam-kit.dts
+F: arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi
F: arch/arm/dts/imx6ul-isiot.dtsi
+F: arch/arm/dts/imx6ul-isiot-u-boot.dtsi
F: arch/arm/dts/imx6ul-isiot-emmc.dts
+F: arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi
F: arch/arm/dts/imx6ul-isiot-nand.dts
@@ -31,9 +31,9 @@ BOOT_OFFSET FLASH_OFFSET_STANDARD
#define __ASSEMBLY__
#include <config.h>
-#include "asm/arch-mx6/mx6-ddr.h"
-#include "asm/arch-mx6/iomux.h"
-#include "asm/arch-mx6/crm_regs.h"
+#include "asm/arch-imx6/mx6-ddr.h"
+#include "asm/arch-imx6/iomux.h"
+#include "asm/arch-imx6/crm_regs.h"
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
u-boot,dm-spl property is specific to U-Boot, so move it into *u-boot.dtsi files for relevant i.MX6UL files. This make syncing Linux dts files straight forward. Also update the MAINTAINERS file for dts files. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi | 25 ++++++++++++++++++++++ arch/arm/dts/imx6ul-geam-kit.dts | 4 ---- arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi | 17 +++++++++++++++ arch/arm/dts/imx6ul-isiot-emmc.dts | 2 -- arch/arm/dts/imx6ul-isiot-u-boot.dtsi | 18 ++++++++++++++++ arch/arm/dts/imx6ul-isiot.dtsi | 2 -- arch/arm/dts/imx6ul-u-boot.dtsi | 32 ++++++++++++++++++++++++++++ arch/arm/dts/imx6ul.dtsi | 6 ------ board/engicam/imx6ul/MAINTAINERS | 5 +++++ board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg | 6 +++--- 10 files changed, 100 insertions(+), 17 deletions(-) create mode 100644 arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-isiot-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-u-boot.dtsi