Message ID | 1521110393-31244-3-git-send-email-j-keerthy@ti.com |
---|---|
State | Superseded |
Delegated to: | Tom Rini |
Headers | show |
Series | ARM: AM43xx: Add support for RTC only mode | expand |
On Thu, Mar 15, 2018 at 04:09:53PM +0530, Keerthy wrote: > From: Dave Gerlach <d-gerlach@ti.com> > > Prevent EMIF control of DDR_RESET line on DDR3 am43xx platforms for > am43xx_evm_rtconly_config. Without this DDR is unstable and can become > corrupted after multiple iterations of RTC+DDR mode. > > Signed-off-by: Dave Gerlach <d-gerlach@ti.com> > [j-keerthy@ti.com Ported to latest master branch] > Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index 68c7705..54e11d3 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -95,8 +95,13 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) +#ifndef CONFIG_SPL_RTC_ONLY_SUPPORT /* Allow EMIF to control DDR_RESET */ writel(0x00000000, &ddrctrl->ddrioctrl); +#else + /* Override EMIF DDR_RESET control */ + writel(0x80000000, &ddrctrl->ddrioctrl); +#endif /* CONFIG_SPL_RTC_ONLY_SUPPORT */ #endif /* Program EMIF instance */