ARM: dts: sun8i-h3: Add Mali node

Message ID 1520936205-64723-1-git-send-email-giulio.benetti@micronovasrl.com
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  • ARM: dts: sun8i-h3: Add Mali node
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Commit Message

Giulio Benetti March 13, 2018, 10:16 a.m.
The H3 has an ARM Mali 400 GPU, so add binding to our DT.

Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
---
 .../devicetree/bindings/gpu/arm,mali-utgard.txt    |  1 +
 arch/arm/boot/dts/sun8i-h3.dtsi                    | 27 ++++++++++++++++++++++
 2 files changed, 28 insertions(+)

Comments

Maxime Ripard March 14, 2018, 8:05 a.m. | #1
On Tue, Mar 13, 2018 at 11:16:45AM +0100, Giulio Benetti wrote:
> The H3 has an ARM Mali 400 GPU, so add binding to our DT.
> 
> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>

How was this tested?

Is there any specific reason not to share it with the H5?

Maxime
Giulio Benetti March 14, 2018, 10:16 a.m. | #2
Hi,

Il 14/03/2018 09:05, Maxime Ripard ha scritto:
> On Tue, Mar 13, 2018 at 11:16:45AM +0100, Giulio Benetti wrote:
>> The H3 has an ARM Mali 400 GPU, so add binding to our DT.
>>
>> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
> 
> How was this tested?

I wanted you asked me about this to ask you:
if I can't test it on HW, but others tested it all around,
for example using this patch:
https://github.com/armbian/build/blob/master/patch/kernel/sunxi-next/32-h3-DT-add-mali-node.patch

Is it enough? Or do I have to test it directly?
Or maybe I can invite those people to tag this patch as tested-by ?

> 
> Is there any specific reason not to share it with the H5?

Yes, H5 has dual GPU but quad PP and on IRQ you can clearly see:
- GPU_GP
- GPU_GPMMU
- GPU_PMU
- GPU_PP
- GPU_PP0
- GPU_PPMMU0
- GPU_PP1
- GPU_PPMMU1
- GPU_PP2
- GPU_PPMMU2
- GPU_PP3
- GPU_PPMMU3

So I think they should be placed in specific dts files.
What do you think?

Thanks

> 
> Maxime
>
Rob Herring March 18, 2018, 12:49 p.m. | #3
On Tue, Mar 13, 2018 at 11:16:45AM +0100, Giulio Benetti wrote:
> The H3 has an ARM Mali 400 GPU, so add binding to our DT.
> 
> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
> ---
>  .../devicetree/bindings/gpu/arm,mali-utgard.txt    |  1 +
>  arch/arm/boot/dts/sun8i-h3.dtsi                    | 27 ++++++++++++++++++++++
>  2 files changed, 28 insertions(+)

Reviewed-by: Rob Herring <robh@kernel.org>

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Maxime Ripard March 18, 2018, 9:57 p.m. | #4
On Tue, Mar 13, 2018 at 11:16:45AM +0100, Giulio Benetti wrote:
> The H3 has an ARM Mali 400 GPU, so add binding to our DT.
> 
> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>

Applied, thanks!
Maxime

Patch

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
index ad87654..c1f65d1 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -10,6 +10,7 @@  Required properties:
     * And, optionally, one of the vendor specific compatible:
       + allwinner,sun4i-a10-mali
       + allwinner,sun7i-a20-mali
+      + allwinner,sun8i-h3-mali
       + allwinner,sun50i-h5-mali
       + amlogic,meson-gxbb-mali
       + amlogic,meson-gxl-mali
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 8495dee..10da8ed 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -79,6 +79,33 @@ 
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+
+	soc {
+		mali: gpu@1c40000 {
+			compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
+			reg = <0x01c40000 0x10000>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gp",
+					  "gpmmu",
+					  "pp0",
+					  "ppmmu0",
+					  "pp1",
+					  "ppmmu1",
+					  "pmu";
+			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+			clock-names = "bus", "core";
+			resets = <&ccu RST_BUS_GPU>;
+
+			assigned-clocks = <&ccu CLK_GPU>;
+			assigned-clock-rates = <384000000>;
+		};
+	};
 };
 
 &ccu {