From patchwork Mon Mar 12 09:46:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 884384 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 400CwN0Llrz9sQn for ; Mon, 12 Mar 2018 20:53:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id AE1E3C21D8A; Mon, 12 Mar 2018 09:51:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8B2A9C21E56; Mon, 12 Mar 2018 09:47:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3AD2DC21E39; Mon, 12 Mar 2018 09:46:47 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id BB258C21DFA for ; Mon, 12 Mar 2018 09:46:43 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w2C9iCfR016512; Mon, 12 Mar 2018 10:46:41 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2gm5c88yrq-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 12 Mar 2018 10:46:41 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DBA8243; Mon, 12 Mar 2018 09:46:40 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A09B324A6; Mon, 12 Mar 2018 09:46:40 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 12 Mar 2018 10:46:40 +0100 Received: from localhost (10.201.23.85) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 12 Mar 2018 10:46:40 +0100 From: Patrick Delaunay To: Date: Mon, 12 Mar 2018 10:46:14 +0100 Message-ID: <1520847978-24321-12-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520847978-24321-1-git-send-email-patrick.delaunay@st.com> References: <1520847978-24321-1-git-send-email-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-03-12_05:, , signatures=0 Cc: benjamin.gaignard@st.com, Elaine Zhang Subject: [U-Boot] [PATCH v2 11/15] reset: stm32: adapt driver for stm32mp1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" - move to livetree and allow to get address to parent - add stm32mp1 compatible for probe Signed-off-by: Patrick Delaunay --- Changes in v2: None drivers/reset/Kconfig | 2 +- drivers/reset/stm32-reset.c | 36 ++++++++++++++++++++++++++++++------ 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 3964b9e..71a786b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -30,7 +30,7 @@ config STI_RESET config STM32_RESET bool "Enable the STM32 reset" - depends on STM32 + depends on STM32 || ARCH_STM32MP help Support for reset controllers on STMicroelectronics STM32 family SoCs. This resset driver is compatible with STM32 F4/F7 and H7 SoCs. diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c index b266f46..e98f34b 100644 --- a/drivers/reset/stm32-reset.c +++ b/drivers/reset/stm32-reset.c @@ -11,7 +11,13 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; +/* reset clear offset for STM32MP RCC */ +#define RCC_CL 0x4 + +enum rcc_type { + RCC_STM32 = 0, + RCC_STM32MP, +}; struct stm32_reset_priv { fdt_addr_t base; @@ -35,7 +41,11 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl) debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__, reset_ctl->id, bank, offset); - setbits_le32(priv->base + bank, BIT(offset)); + if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP) + /* reset assert is done in rcc set register */ + writel(BIT(offset), priv->base + bank); + else + setbits_le32(priv->base + bank, BIT(offset)); return 0; } @@ -48,7 +58,11 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl) debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__, reset_ctl->id, bank, offset); - clrbits_le32(priv->base + bank, BIT(offset)); + if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP) + /* reset deassert is done in rcc clr register */ + writel(BIT(offset), priv->base + bank + RCC_CL); + else + clrbits_le32(priv->base + bank, BIT(offset)); return 0; } @@ -64,16 +78,26 @@ static int stm32_reset_probe(struct udevice *dev) { struct stm32_reset_priv *priv = dev_get_priv(dev); - priv->base = devfdt_get_addr(dev); - if (priv->base == FDT_ADDR_T_NONE) - return -EINVAL; + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) { + /* for MFD, get address of parent */ + priv->base = dev_read_addr(dev->parent); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + } return 0; } +static const struct udevice_id stm32_reset_ids[] = { + { .compatible = "st,stm32mp1-rcc-rst", .data = RCC_STM32MP }, + { } +}; + U_BOOT_DRIVER(stm32_rcc_reset) = { .name = "stm32_rcc_reset", .id = UCLASS_RESET, + .of_match = stm32_reset_ids, .probe = stm32_reset_probe, .priv_auto_alloc_size = sizeof(struct stm32_reset_priv), .ops = &stm32_reset_ops,