From patchwork Fri Mar 25 18:27:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 88406 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 61B6AB6F90 for ; Sat, 26 Mar 2011 05:28:00 +1100 (EST) Received: (qmail 27822 invoked by alias); 25 Mar 2011 18:27:59 -0000 Received: (qmail 27814 invoked by uid 22791); 25 Mar 2011 18:27:58 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-wy0-f175.google.com (HELO mail-wy0-f175.google.com) (74.125.82.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 25 Mar 2011 18:27:54 +0000 Received: by wye20 with SMTP id 20so871371wye.20 for ; Fri, 25 Mar 2011 11:27:53 -0700 (PDT) Received: by 10.227.200.75 with SMTP id ev11mr1045872wbb.56.1301077673113; Fri, 25 Mar 2011 11:27:53 -0700 (PDT) Received: from richards-thinkpad (gbibp9ph1--blueice2n1.emea.ibm.com [195.212.29.75]) by mx.google.com with ESMTPS id u9sm577484wbg.17.2011.03.25.11.27.51 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 25 Mar 2011 11:27:52 -0700 (PDT) From: Richard Sandiford To: Richard Earnshaw Mail-Followup-To: Richard Earnshaw , gcc-patches@gcc.gnu.org, patches@linaro.org, richard.sandiford@linaro.org Cc: gcc-patches@gcc.gnu.org, patches@linaro.org Subject: Re: Tighten ARM's CANNOT_CHANGE_MODE_CLASS References: <1300985270.12868.95.camel@e102346-lin.cambridge.arm.com> <1301051683.28571.10.camel@e102346-lin.cambridge.arm.com> Date: Fri, 25 Mar 2011 18:27:49 +0000 In-Reply-To: <1301051683.28571.10.camel@e102346-lin.cambridge.arm.com> (Richard Earnshaw's message of "Fri, 25 Mar 2011 11:14:43 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1 (gnu/linux) MIME-Version: 1.0 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Richard Earnshaw writes: >> gcc/ >> * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Restrict FPA_REGS >> case to VFPv1. >> > > I think adding a comment that VFPv1 would require a restriction but that > that isn't supported would be useful. Then if the worst happens it will > be one less bug to go track down. > > OK with that change. Thanks. Here's what I installed. Richard gcc/ * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Restrict FPA_REGS case to VFPv1. Index: gcc/config/arm/arm.h =================================================================== --- gcc/config/arm/arm.h 2011-03-25 18:19:45.000000000 +0000 +++ gcc/config/arm/arm.h 2011-03-25 18:26:13.000000000 +0000 @@ -1167,12 +1167,12 @@ #define IRA_COVER_CLASSES \ } /* FPA registers can't do subreg as all values are reformatted to internal - precision. VFP registers may only be accessed in the mode they - were set. */ -#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ - (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ - ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ - || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ + precision. In VFPv1, VFP registers could only be accessed in the mode + they were set, so subregs would be invalid there too. However, we don't + support VFPv1 at the moment, and the restriction was lifted in VFPv2. */ +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ : 0) /* The class value for index registers, and the one for base regs. */