| Message ID | 1520501697-22202-1-git-send-email-ping.bai@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v4,1/3] ARM: imx: Add basic msl support for imx6sll | expand |
On Thu, Mar 08, 2018 at 05:34:56PM +0800, Bai Ping wrote: > Add low level debug support for i.MX6SLL. > > Signed-off-by: Bai Ping <ping.bai@nxp.com> With earlycon support in place, I'm not sure we want to add more SoC low-level debug port. Shawn > --- > change v1->v2: > - no > change v2->v3: > - no > change v3->v4: > - no > --- > arch/arm/Kconfig.debug | 9 +++++++++ > arch/arm/include/debug/imx-uart.h | 10 ++++++++++ > 2 files changed, 19 insertions(+) > > diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug > index 78a6470..2197239 100644 > --- a/arch/arm/Kconfig.debug > +++ b/arch/arm/Kconfig.debug > @@ -451,6 +451,13 @@ choice > Say Y here if you want kernel low-level debugging support > on i.MX6SL. > > + config DEBUG_IMX6SLL_UART > + bool "i.MX6SLL Debug UART" > + depends on SOC_IMX6SLL > + help > + Say Y here if you want kernel low-level debugging support > + on i.MX6SLL. > + > config DEBUG_IMX6SX_UART > bool "i.MX6SX Debug UART" > depends on SOC_IMX6SX > @@ -1429,6 +1436,7 @@ config DEBUG_IMX_UART_PORT > DEBUG_IMX53_UART || \ > DEBUG_IMX6Q_UART || \ > DEBUG_IMX6SL_UART || \ > + DEBUG_IMX6SLL_UART || \ > DEBUG_IMX6SX_UART || \ > DEBUG_IMX6UL_UART || \ > DEBUG_IMX7D_UART > @@ -1483,6 +1491,7 @@ config DEBUG_LL_INCLUDE > DEBUG_IMX53_UART ||\ > DEBUG_IMX6Q_UART || \ > DEBUG_IMX6SL_UART || \ > + DEBUG_IMX6SLL_UART || \ > DEBUG_IMX6SX_UART || \ > DEBUG_IMX6UL_UART || \ > DEBUG_IMX7D_UART > diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h > index bce58e9..24e60ce 100644 > --- a/arch/arm/include/debug/imx-uart.h > +++ b/arch/arm/include/debug/imx-uart.h > @@ -81,6 +81,14 @@ > #define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR > #define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n) > > +#define IMX6SLL_UART1_BASE_ADDR 0x02020000 > +#define IMX6SLL_UART2_BASE_ADDR 0x02024000 > +#define IMX6SLL_UART3_BASE_ADDR 0x02034000 > +#define IMX6SLL_UART4_BASE_ADDR 0x02018000 > +#define IMX6SLL_UART5_BASE_ADDR 0x021f4000 > +#define IMX6SLL_UART_BASE_ADDR(n) IMX6SLL_UART##n##_BASE_ADDR > +#define IMX6SLL_UART_BASE(n) IMX6SLL_UART_BASE_ADDR(n) > + > #define IMX6SX_UART1_BASE_ADDR 0x02020000 > #define IMX6SX_UART2_BASE_ADDR 0x021e8000 > #define IMX6SX_UART3_BASE_ADDR 0x021ec000 > @@ -133,6 +141,8 @@ > #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) > #elif defined(CONFIG_DEBUG_IMX6SL_UART) > #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) > +#elif defined(CONFIG_DEBUG_IMX6SLL_UART) > +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SLL) > #elif defined(CONFIG_DEBUG_IMX6SX_UART) > #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX) > #elif defined(CONFIG_DEBUG_IMX6UL_UART) > -- > 1.9.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Thu, Mar 08, 2018 at 05:34:55PM +0800, Bai Ping wrote: > Add basic MSL support for i.MX6SLL. > > The i.MX 6SoloLiteLite application processors are NXP's latest > additions to a growing family of multimedia-focused products > offering high-performance processing optimized for lowest power > consumption. The i.MX 6SoloLiteLite processors feature NXP's advanced > implementation of the ARM Cortex-A9 core, which can be interfaced > with LPDDR3 and LPDDR2 DRAM memory devices. > > Signed-off-by: Bai Ping <ping.bai@nxp.com> > --- > change from v1->v2: > - no > change from v2->v3: > - no > change from v3->v4: > - fix build warning > --- > arch/arm/mach-imx/Kconfig | 7 +++++++ > arch/arm/mach-imx/Makefile | 1 + > arch/arm/mach-imx/cpu.c | 3 +++ > arch/arm/mach-imx/cpuidle-imx6sl.c | 7 +++++-- > arch/arm/mach-imx/mach-imx6sl.c | 10 ++++++++-- > arch/arm/mach-imx/mxc.h | 6 ++++++ > 6 files changed, 30 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig > index 782699e..8e3a618 100644 > --- a/arch/arm/mach-imx/Kconfig > +++ b/arch/arm/mach-imx/Kconfig > @@ -512,6 +512,13 @@ config SOC_IMX6SL > help > This enables support for Freescale i.MX6 SoloLite processor. > > +config SOC_IMX6SLL > + bool "i.MX6 SoloLiteLite support" > + select SOC_IMX6 > + > + help > + This enables support for Freescale i.MX6 SoloLiteLite processor. > + > config SOC_IMX6SX > bool "i.MX6 SoloX support" > select PINCTRL_IMX6SX > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > index 8ff7105..c5caecb 100644 > --- a/arch/arm/mach-imx/Makefile > +++ b/arch/arm/mach-imx/Makefile > @@ -78,6 +78,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o > endif > obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o > obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o > +obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o > obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o > obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o > obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o > diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c > index d4e55f2..32969f3 100644 > --- a/arch/arm/mach-imx/cpu.c > +++ b/arch/arm/mach-imx/cpu.c > @@ -135,6 +135,9 @@ struct device * __init imx_soc_device_init(void) > case MXC_CPU_IMX6ULL: > soc_id = "i.MX6ULL"; > break; > + case MXC_CPU_IMX6SLL: > + soc_id = "i.MX6SLL"; > + break; > case MXC_CPU_IMX7D: > soc_id = "i.MX7D"; > break; > diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c > index 8d866fb..124f982 100644 > --- a/arch/arm/mach-imx/cpuidle-imx6sl.c > +++ b/arch/arm/mach-imx/cpuidle-imx6sl.c > @@ -11,6 +11,7 @@ > #include <asm/cpuidle.h> > > #include "common.h" > +#include "hardware.h" > #include "cpuidle.h" The headers should be sorted alphabetically. > > static int imx6sl_enter_wait(struct cpuidle_device *dev, > @@ -21,9 +22,11 @@ static int imx6sl_enter_wait(struct cpuidle_device *dev, > * Software workaround for ERR005311, see function > * description for details. > */ > - imx6sl_set_wait_clk(true); > + if (cpu_is_imx6sl()) > + imx6sl_set_wait_clk(true); > cpu_do_idle(); > - imx6sl_set_wait_clk(false); > + if (cpu_is_imx6sl()) > + imx6sl_set_wait_clk(false); > imx6_set_lpm(WAIT_CLOCKED); > > return index; > diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c > index 0408490..462ed9c 100644 > --- a/arch/arm/mach-imx/mach-imx6sl.c > +++ b/arch/arm/mach-imx/mach-imx6sl.c > @@ -17,6 +17,7 @@ > #include <asm/mach/map.h> > > #include "common.h" > +#include "hardware.h" > #include "cpuidle.h" Ditto. I fixed them up and applied the patch. Shawn > > static void __init imx6sl_fec_init(void) > @@ -54,7 +55,8 @@ static void __init imx6sl_init_machine(void) > > of_platform_default_populate(NULL, NULL, parent); > > - imx6sl_fec_init(); > + if (cpu_is_imx6sl()) > + imx6sl_fec_init(); > imx_anatop_init(); > imx6sl_pm_init(); > } > @@ -66,11 +68,15 @@ static void __init imx6sl_init_irq(void) > imx_init_l2cache(); > imx_src_init(); > irqchip_init(); > - imx6_pm_ccm_init("fsl,imx6sl-ccm"); > + if (cpu_is_imx6sl()) > + imx6_pm_ccm_init("fsl,imx6sl-ccm"); > + else > + imx6_pm_ccm_init("fsl,imx6sll-ccm"); > } > > static const char * const imx6sl_dt_compat[] __initconst = { > "fsl,imx6sl", > + "fsl,imx6sll", > NULL, > }; > > diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h > index e00d626..026e2ca 100644 > --- a/arch/arm/mach-imx/mxc.h > +++ b/arch/arm/mach-imx/mxc.h > @@ -40,6 +40,7 @@ > #define MXC_CPU_IMX6Q 0x63 > #define MXC_CPU_IMX6UL 0x64 > #define MXC_CPU_IMX6ULL 0x65 > +#define MXC_CPU_IMX6SLL 0x67 > #define MXC_CPU_IMX7D 0x72 > > #define IMX_DDR_TYPE_LPDDR2 1 > @@ -79,6 +80,11 @@ static inline bool cpu_is_imx6ull(void) > return __mxc_cpu_type == MXC_CPU_IMX6ULL; > } > > +static inline bool cpu_is_imx6sll(void) > +{ > + return __mxc_cpu_type == MXC_CPU_IMX6SLL; > +} > + > static inline bool cpu_is_imx6q(void) > { > return __mxc_cpu_type == MXC_CPU_IMX6Q; > -- > 1.9.1 >
On Thu, Mar 08, 2018 at 05:34:57PM +0800, Bai Ping wrote: > Add gpt timer support for i.MX6SLL. > > Signed-off-by: Bai Ping <ping.bai@nxp.com> The patch should be sent to clocksource maintainer. > --- > change v1->v2: > - no > change v2->v3: > - no > change v3->v4: > - no > --- > drivers/clocksource/timer-imx-gpt.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clocksource/timer-imx-gpt.c b/drivers/clocksource/timer-imx-gpt.c > index 6ec6d79..57b7eab 100644 > --- a/drivers/clocksource/timer-imx-gpt.c > +++ b/drivers/clocksource/timer-imx-gpt.c > @@ -557,3 +557,4 @@ static int __init imx6dl_timer_init_dt(struct device_node *np) > TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt); > TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt); > TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt); > +TIMER_OF_DECLARE(imx6sll_timer, "fsl,imx6sll-gpt", imx6dl_timer_init_dt); I'm wondering if we can save this change by letting the compatible of imx6sll-gpt fall on "fsl,imx6dl-gpt" in DT. Shawn
> Subject: Re: [PATCH v4 3/3] driver: clocksource: add gpt timer for imx6sll > > On Thu, Mar 08, 2018 at 05:34:57PM +0800, Bai Ping wrote: > > Add gpt timer support for i.MX6SLL. > > > > Signed-off-by: Bai Ping <ping.bai@nxp.com> > > The patch should be sent to clocksource maintainer. > > > --- > > change v1->v2: > > - no > > change v2->v3: > > - no > > change v3->v4: > > - no > > --- > > drivers/clocksource/timer-imx-gpt.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/clocksource/timer-imx-gpt.c > > b/drivers/clocksource/timer-imx-gpt.c > > index 6ec6d79..57b7eab 100644 > > --- a/drivers/clocksource/timer-imx-gpt.c > > +++ b/drivers/clocksource/timer-imx-gpt.c > > @@ -557,3 +557,4 @@ static int __init imx6dl_timer_init_dt(struct > > device_node *np) TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", > > imx6dl_timer_init_dt); TIMER_OF_DECLARE(imx6sl_timer, > > "fsl,imx6sl-gpt", imx6dl_timer_init_dt); > > TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", > > imx6dl_timer_init_dt); > > +TIMER_OF_DECLARE(imx6sll_timer, "fsl,imx6sll-gpt", > > +imx6dl_timer_init_dt); > > I'm wondering if we can save this change by letting the compatible of imx6sll-gpt > fall on "fsl,imx6dl-gpt" in DT. > Sure, this patch can be dropped. I will update the dts compatible string accordingly. Jacky > Shawn
> Subject: Re: [PATCH v4 2/3] ARM: debug: Add low level debug support for imx6sll > > On Thu, Mar 08, 2018 at 05:34:56PM +0800, Bai Ping wrote: > > Add low level debug support for i.MX6SLL. > > > > Signed-off-by: Bai Ping <ping.bai@nxp.com> > > With earlycon support in place, I'm not sure we want to add more SoC low-level > debug port. > OK, maybe we can drop this patch. Jacky > Shawn > > > --- > > change v1->v2: > > - no > > change v2->v3: > > - no > > change v3->v4: > > - no > > --- > > arch/arm/Kconfig.debug | 9 +++++++++ > > arch/arm/include/debug/imx-uart.h | 10 ++++++++++ > > 2 files changed, 19 insertions(+) > > > > diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index > > 78a6470..2197239 100644 > > --- a/arch/arm/Kconfig.debug > > +++ b/arch/arm/Kconfig.debug > > @@ -451,6 +451,13 @@ choice > > Say Y here if you want kernel low-level debugging support > > on i.MX6SL. > > > > + config DEBUG_IMX6SLL_UART > > + bool "i.MX6SLL Debug UART" > > + depends on SOC_IMX6SLL > > + help > > + Say Y here if you want kernel low-level debugging support > > + on i.MX6SLL. > > + > > config DEBUG_IMX6SX_UART > > bool "i.MX6SX Debug UART" > > depends on SOC_IMX6SX > > @@ -1429,6 +1436,7 @@ config DEBUG_IMX_UART_PORT > > DEBUG_IMX53_UART || \ > > DEBUG_IMX6Q_UART || \ > > DEBUG_IMX6SL_UART || \ > > + DEBUG_IMX6SLL_UART || \ > > DEBUG_IMX6SX_UART || \ > > DEBUG_IMX6UL_UART || \ > > DEBUG_IMX7D_UART > > @@ -1483,6 +1491,7 @@ config DEBUG_LL_INCLUDE > > DEBUG_IMX53_UART ||\ > > DEBUG_IMX6Q_UART || \ > > DEBUG_IMX6SL_UART || \ > > + DEBUG_IMX6SLL_UART || \ > > DEBUG_IMX6SX_UART || \ > > DEBUG_IMX6UL_UART || \ > > DEBUG_IMX7D_UART > > diff --git a/arch/arm/include/debug/imx-uart.h > > b/arch/arm/include/debug/imx-uart.h > > index bce58e9..24e60ce 100644 > > --- a/arch/arm/include/debug/imx-uart.h > > +++ b/arch/arm/include/debug/imx-uart.h > > @@ -81,6 +81,14 @@ > > #define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR > > #define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n) > > > > +#define IMX6SLL_UART1_BASE_ADDR 0x02020000 #define > > +IMX6SLL_UART2_BASE_ADDR 0x02024000 #define > IMX6SLL_UART3_BASE_ADDR > > +0x02034000 #define IMX6SLL_UART4_BASE_ADDR 0x02018000 #define > > +IMX6SLL_UART5_BASE_ADDR 0x021f4000 #define > IMX6SLL_UART_BASE_ADDR(n) > > +IMX6SLL_UART##n##_BASE_ADDR > > +#define IMX6SLL_UART_BASE(n) IMX6SLL_UART_BASE_ADDR(n) > > + > > #define IMX6SX_UART1_BASE_ADDR 0x02020000 > > #define IMX6SX_UART2_BASE_ADDR 0x021e8000 > > #define IMX6SX_UART3_BASE_ADDR 0x021ec000 > > @@ -133,6 +141,8 @@ > > #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) > > #elif defined(CONFIG_DEBUG_IMX6SL_UART) > > #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) > > +#elif defined(CONFIG_DEBUG_IMX6SLL_UART) > > +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SLL) > > #elif defined(CONFIG_DEBUG_IMX6SX_UART) > > #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX) > > #elif defined(CONFIG_DEBUG_IMX6UL_UART) > > -- > > 1.9.1 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flist > > > s.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&data=02%7C01%7 > > > Cping.bai%40nxp.com%7Cff87034a5489455501c308d5855bdd78%7C686ea1d3 > bc2b4 > > > c6fa92cd99c5c301635%7C0%7C0%7C636561551970392594&sdata=zDX%2Bgt > WfguB5B > > d7wNjd0rl5coxrVR1eLekMBc%2BIdnEg%3D&reserved=0
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 782699e..8e3a618 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -512,6 +512,13 @@ config SOC_IMX6SL help This enables support for Freescale i.MX6 SoloLite processor. +config SOC_IMX6SLL + bool "i.MX6 SoloLiteLite support" + select SOC_IMX6 + + help + This enables support for Freescale i.MX6 SoloLiteLite processor. + config SOC_IMX6SX bool "i.MX6 SoloX support" select PINCTRL_IMX6SX diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 8ff7105..c5caecb 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o endif obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o +obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index d4e55f2..32969f3 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -135,6 +135,9 @@ struct device * __init imx_soc_device_init(void) case MXC_CPU_IMX6ULL: soc_id = "i.MX6ULL"; break; + case MXC_CPU_IMX6SLL: + soc_id = "i.MX6SLL"; + break; case MXC_CPU_IMX7D: soc_id = "i.MX7D"; break; diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c index 8d866fb..124f982 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sl.c +++ b/arch/arm/mach-imx/cpuidle-imx6sl.c @@ -11,6 +11,7 @@ #include <asm/cpuidle.h> #include "common.h" +#include "hardware.h" #include "cpuidle.h" static int imx6sl_enter_wait(struct cpuidle_device *dev, @@ -21,9 +22,11 @@ static int imx6sl_enter_wait(struct cpuidle_device *dev, * Software workaround for ERR005311, see function * description for details. */ - imx6sl_set_wait_clk(true); + if (cpu_is_imx6sl()) + imx6sl_set_wait_clk(true); cpu_do_idle(); - imx6sl_set_wait_clk(false); + if (cpu_is_imx6sl()) + imx6sl_set_wait_clk(false); imx6_set_lpm(WAIT_CLOCKED); return index; diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 0408490..462ed9c 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -17,6 +17,7 @@ #include <asm/mach/map.h> #include "common.h" +#include "hardware.h" #include "cpuidle.h" static void __init imx6sl_fec_init(void) @@ -54,7 +55,8 @@ static void __init imx6sl_init_machine(void) of_platform_default_populate(NULL, NULL, parent); - imx6sl_fec_init(); + if (cpu_is_imx6sl()) + imx6sl_fec_init(); imx_anatop_init(); imx6sl_pm_init(); } @@ -66,11 +68,15 @@ static void __init imx6sl_init_irq(void) imx_init_l2cache(); imx_src_init(); irqchip_init(); - imx6_pm_ccm_init("fsl,imx6sl-ccm"); + if (cpu_is_imx6sl()) + imx6_pm_ccm_init("fsl,imx6sl-ccm"); + else + imx6_pm_ccm_init("fsl,imx6sll-ccm"); } static const char * const imx6sl_dt_compat[] __initconst = { "fsl,imx6sl", + "fsl,imx6sll", NULL, }; diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index e00d626..026e2ca 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -40,6 +40,7 @@ #define MXC_CPU_IMX6Q 0x63 #define MXC_CPU_IMX6UL 0x64 #define MXC_CPU_IMX6ULL 0x65 +#define MXC_CPU_IMX6SLL 0x67 #define MXC_CPU_IMX7D 0x72 #define IMX_DDR_TYPE_LPDDR2 1 @@ -79,6 +80,11 @@ static inline bool cpu_is_imx6ull(void) return __mxc_cpu_type == MXC_CPU_IMX6ULL; } +static inline bool cpu_is_imx6sll(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6SLL; +} + static inline bool cpu_is_imx6q(void) { return __mxc_cpu_type == MXC_CPU_IMX6Q;
Add basic MSL support for i.MX6SLL. The i.MX 6SoloLiteLite application processors are NXP's latest additions to a growing family of multimedia-focused products offering high-performance processing optimized for lowest power consumption. The i.MX 6SoloLiteLite processors feature NXP's advanced implementation of the ARM Cortex-A9 core, which can be interfaced with LPDDR3 and LPDDR2 DRAM memory devices. Signed-off-by: Bai Ping <ping.bai@nxp.com> --- change from v1->v2: - no change from v2->v3: - no change from v3->v4: - fix build warning --- arch/arm/mach-imx/Kconfig | 7 +++++++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/cpu.c | 3 +++ arch/arm/mach-imx/cpuidle-imx6sl.c | 7 +++++-- arch/arm/mach-imx/mach-imx6sl.c | 10 ++++++++-- arch/arm/mach-imx/mxc.h | 6 ++++++ 6 files changed, 30 insertions(+), 4 deletions(-)