| Message ID | 20180307215216.10418-11-marek.behun@nic.cz |
|---|---|
| State | Superseded |
| Delegated to: | Stefan Roese |
| Headers | show |
| Series | More support for Armada 37xx boards | expand |
On 07.03.2018 22:52, Marek Behún wrote: > Currently comphy_mux supports only trivial order of nodes in pin > selector register, that is lane N on position N*bitcount. > > Add support for nontrivial order, with map stored in device tree > property mux-lane-order. > > This is needed for Armada 37xx. > > Signed-off-by: Marek Behun <marek.behun@nic.cz> I currently have no overview of the (ongoing ?) PHY support for A37xx in Linux. I know that we don't match the Linux upstream dts files in U-Boot currently. But we should strive to move to the "official" DT properties here. If there is nothing available right now, then I can take this approach for now. But we should keep in mind, to perhaps move / change to some other implementation later. Thanks, Stefan > --- > drivers/phy/marvell/comphy.h | 1 + > drivers/phy/marvell/comphy_core.c | 4 ++++ > drivers/phy/marvell/comphy_mux.c | 15 ++++++++++++--- > 3 files changed, 17 insertions(+), 3 deletions(-) > > diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h > index c9b94a4c5e..32e0a1e652 100644 > --- a/drivers/phy/marvell/comphy.h > +++ b/drivers/phy/marvell/comphy.h > @@ -97,6 +97,7 @@ struct chip_serdes_phy_config { > void __iomem *hpipe3_base_addr; > u32 comphy_lanes_count; > u32 comphy_mux_bitcount; > + const fdt32_t *comphy_mux_lane_order; > u32 cp_index; > }; > > diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c > index 426db30f73..1e5664c435 100644 > --- a/drivers/phy/marvell/comphy_core.c > +++ b/drivers/phy/marvell/comphy_core.c > @@ -135,6 +135,10 @@ static int comphy_probe(struct udevice *dev) > return -EINVAL; > } > > + chip_cfg->comphy_mux_lane_order = > + fdtdec_locate_array(blob, node, "mux-lane-order", > + chip_cfg->comphy_lanes_count); > + > if (device_is_compatible(dev, "marvell,comphy-armada-3700")) > chip_cfg->ptr_comphy_chip_init = comphy_a3700_init; > > diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c > index b036fb13b9..a8b07fdc98 100644 > --- a/drivers/phy/marvell/comphy_mux.c > +++ b/drivers/phy/marvell/comphy_mux.c > @@ -79,7 +79,8 @@ static u32 comphy_mux_get_mux_value(struct comphy_mux_data *mux_data, > static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, > struct comphy_map *comphy_map_data, > int comphy_max_lanes, > - void __iomem *selector_base, u32 bitcount) > + void __iomem *selector_base, > + const fdt32_t *mux_lane_order, u32 bitcount) > { > u32 lane, value, offset, mask; > > @@ -90,7 +91,13 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, > if (comphy_map_data->type == PHY_TYPE_IGNORE) > continue; > > - offset = lane * bitcount; > + /* if the order of nodes in selector base register is > + nontrivial, use mapping from mux_lane_order */ > + if (mux_lane_order) > + offset = fdt32_to_cpu(mux_lane_order[lane]) * bitcount; > + else > + offset = lane * bitcount; > + > mask = (((1 << bitcount) - 1) << offset); > value = (comphy_mux_get_mux_value(mux_data, > comphy_map_data->type, > @@ -106,6 +113,7 @@ void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg, > void __iomem *selector_base) > { > struct comphy_mux_data *mux_data; > + const fdt32_t *mux_lane_order; > u32 mux_bitcount; > u32 comphy_max_lanes; > > @@ -113,13 +121,14 @@ void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg, > > comphy_max_lanes = chip_cfg->comphy_lanes_count; > mux_data = chip_cfg->mux_data; > + mux_lane_order = chip_cfg->comphy_mux_lane_order; > mux_bitcount = chip_cfg->comphy_mux_bitcount; > > /* check if the configuration is valid */ > comphy_mux_check_config(mux_data, comphy_map_data, comphy_max_lanes); > /* Init COMPHY selectors */ > comphy_mux_reg_write(mux_data, comphy_map_data, comphy_max_lanes, > - selector_base, mux_bitcount); > + selector_base, mux_lane_order, mux_bitcount); > > debug_exit(); > } > Viele Grüße, Stefan
On Wed, 21 Mar 2018 10:19:16 +0100 Stefan Roese <sr@denx.de> wrote: > I currently have no overview of the (ongoing ?) PHY support for > A37xx in Linux. I know that we don't match the Linux upstream dts > files in U-Boot currently. But we should strive to move to the > "official" DT properties here. > > If there is nothing available right now, then I can take this > approach for now. But we should keep in mind, to perhaps move / > change to some other implementation later. I too don't have any overview, a quick googling found nothing on mailing lists. I think that maybe no one is doing any work to code the a37xx comphy driver for kernel. I am thinking about writing one myself and trying to send it to mailing list. Which mailing list do you think I should send this to? linux-arm-kernel? Marek
diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h index c9b94a4c5e..32e0a1e652 100644 --- a/drivers/phy/marvell/comphy.h +++ b/drivers/phy/marvell/comphy.h @@ -97,6 +97,7 @@ struct chip_serdes_phy_config { void __iomem *hpipe3_base_addr; u32 comphy_lanes_count; u32 comphy_mux_bitcount; + const fdt32_t *comphy_mux_lane_order; u32 cp_index; }; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 426db30f73..1e5664c435 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -135,6 +135,10 @@ static int comphy_probe(struct udevice *dev) return -EINVAL; } + chip_cfg->comphy_mux_lane_order = + fdtdec_locate_array(blob, node, "mux-lane-order", + chip_cfg->comphy_lanes_count); + if (device_is_compatible(dev, "marvell,comphy-armada-3700")) chip_cfg->ptr_comphy_chip_init = comphy_a3700_init; diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index b036fb13b9..a8b07fdc98 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -79,7 +79,8 @@ static u32 comphy_mux_get_mux_value(struct comphy_mux_data *mux_data, static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, struct comphy_map *comphy_map_data, int comphy_max_lanes, - void __iomem *selector_base, u32 bitcount) + void __iomem *selector_base, + const fdt32_t *mux_lane_order, u32 bitcount) { u32 lane, value, offset, mask; @@ -90,7 +91,13 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, if (comphy_map_data->type == PHY_TYPE_IGNORE) continue; - offset = lane * bitcount; + /* if the order of nodes in selector base register is + nontrivial, use mapping from mux_lane_order */ + if (mux_lane_order) + offset = fdt32_to_cpu(mux_lane_order[lane]) * bitcount; + else + offset = lane * bitcount; + mask = (((1 << bitcount) - 1) << offset); value = (comphy_mux_get_mux_value(mux_data, comphy_map_data->type, @@ -106,6 +113,7 @@ void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg, void __iomem *selector_base) { struct comphy_mux_data *mux_data; + const fdt32_t *mux_lane_order; u32 mux_bitcount; u32 comphy_max_lanes; @@ -113,13 +121,14 @@ void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg, comphy_max_lanes = chip_cfg->comphy_lanes_count; mux_data = chip_cfg->mux_data; + mux_lane_order = chip_cfg->comphy_mux_lane_order; mux_bitcount = chip_cfg->comphy_mux_bitcount; /* check if the configuration is valid */ comphy_mux_check_config(mux_data, comphy_map_data, comphy_max_lanes); /* Init COMPHY selectors */ comphy_mux_reg_write(mux_data, comphy_map_data, comphy_max_lanes, - selector_base, mux_bitcount); + selector_base, mux_lane_order, mux_bitcount); debug_exit(); }
Currently comphy_mux supports only trivial order of nodes in pin selector register, that is lane N on position N*bitcount. Add support for nontrivial order, with map stored in device tree property mux-lane-order. This is needed for Armada 37xx. Signed-off-by: Marek Behun <marek.behun@nic.cz> --- drivers/phy/marvell/comphy.h | 1 + drivers/phy/marvell/comphy_core.c | 4 ++++ drivers/phy/marvell/comphy_mux.c | 15 ++++++++++++--- 3 files changed, 17 insertions(+), 3 deletions(-)