[v1,17/22] RISC-V: Hardwire satp to 0 for no-mmu case

Message ID	1520369790-38306-16-git-send-email-mjc@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Michael Clark <mjc@sifive.com> To: qemu-devel@nongnu.org Date: Wed, 7 Mar 2018 09:56:25 +1300 Message-Id: <1520369790-38306-16-git-send-email-mjc@sifive.com> In-Reply-To: <1520369790-38306-1-git-send-email-mjc@sifive.com> References: <1520369790-38306-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v1 17/22] RISC-V: Hardwire satp to 0 for no-mmu case Precedence: list Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches <patches@groups.riscv.org> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	None \| expand [v1,02/22] RISC-V: Replace hardcoded constants with enum values [v1,03/22] RISC-V: Make virt board description match spike [v1,04/22] RISC-V: Use ROM base address and size from memmap [v1,05/22] RISC-V: Remove identity_translate from load_elf [v1,06/22] RISC-V: Mark ROM read-only after copying in code [v1,07/22] RISC-V: Remove unused class definitions [v1,08/22] RISC-V: Make sure rom has space for fdt [v1,09/22] RISC-V: Include hexidecimal in disassembly [v1,10/22] RISC-V: Hold rcu_read_lock when accessing memory [v1,11/22] RISC-V: Improve page table walker spec compliance [v1,12/22] RISC-V: Update E order and I extension order [v1,13/22] RISC-V: Make some header guards more specific [v1,14/22] RISC-V: Make virt header comment title consistent [v1,15/22] RISC-V: Use memory_region_is_ram in pte update [v1,16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection [v1,17/22] RISC-V: Hardwire satp to 0 for no-mmu case [v1,18/22] RISC-V: Remove braces from satp case statement [v1,19/22] RISC-V: riscv-qemu port supports sv39 and sv48 [v1,20/22] RISC-V: vectored traps are optional [v1,21/22] RISC-V: No traps on writes to misa/minstret/mcycle [v1,22/22] RISC-V: Remove support for adhoc X_COP interrupt

Message ID

1520369790-38306-16-git-send-email-mjc@sifive.com

State

New

Headers

From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Date: Wed,  7 Mar 2018 09:56:25 +1300
Message-Id: <1520369790-38306-16-git-send-email-mjc@sifive.com>
In-Reply-To: <1520369790-38306-1-git-send-email-mjc@sifive.com>
References: <1520369790-38306-1-git-send-email-mjc@sifive.com>
Subject: [Qemu-devel] [PATCH v1 17/22] RISC-V: Hardwire satp to 0 for no-mmu
	case
Precedence: list
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches <patches@groups.riscv.org>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

None | expand

Commit Message

Michael Clark March 6, 2018, 8:56 p.m. UTC

satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.

It seems the RISC-V WARL behaviour is preferred to having to
bear trap overhead, versus simply reading back the value and
checking if the write took (saves hundreds of cycles and much
more complex trap handling code).

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/op_helper.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e34715d..dd3e417 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -242,7 +242,7 @@  void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
     }
     case CSR_SATP: /* CSR_SPTBR */ {
         if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
-            goto do_illegal;
+            break;
         }
         if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val_to_write ^ env->sptbr))
         {
@@ -452,7 +452,10 @@  target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
         return env->scounteren;
     case CSR_SCAUSE:
         return env->scause;
-    case CSR_SPTBR:
+    case CSR_SATP: /* CSR_SPTBR */
+        if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+            return 0;
+        }
         if (env->priv_ver >= PRIV_VERSION_1_10_0) {
             return env->satp;
         } else {