[v1,19/22] RISC-V: riscv-qemu port supports sv39 and sv48

Message ID	1520369790-38306-18-git-send-email-mjc@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Michael Clark <mjc@sifive.com> To: qemu-devel@nongnu.org Date: Wed, 7 Mar 2018 09:56:27 +1300 Message-Id: <1520369790-38306-18-git-send-email-mjc@sifive.com> In-Reply-To: <1520369790-38306-1-git-send-email-mjc@sifive.com> References: <1520369790-38306-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48 Precedence: list Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches <patches@groups.riscv.org> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	None \| expand [v1,02/22] RISC-V: Replace hardcoded constants with enum values [v1,03/22] RISC-V: Make virt board description match spike [v1,04/22] RISC-V: Use ROM base address and size from memmap [v1,05/22] RISC-V: Remove identity_translate from load_elf [v1,06/22] RISC-V: Mark ROM read-only after copying in code [v1,07/22] RISC-V: Remove unused class definitions [v1,08/22] RISC-V: Make sure rom has space for fdt [v1,09/22] RISC-V: Include hexidecimal in disassembly [v1,10/22] RISC-V: Hold rcu_read_lock when accessing memory [v1,11/22] RISC-V: Improve page table walker spec compliance [v1,12/22] RISC-V: Update E order and I extension order [v1,13/22] RISC-V: Make some header guards more specific [v1,14/22] RISC-V: Make virt header comment title consistent [v1,15/22] RISC-V: Use memory_region_is_ram in pte update [v1,16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection [v1,17/22] RISC-V: Hardwire satp to 0 for no-mmu case [v1,18/22] RISC-V: Remove braces from satp case statement [v1,19/22] RISC-V: riscv-qemu port supports sv39 and sv48 [v1,20/22] RISC-V: vectored traps are optional [v1,21/22] RISC-V: No traps on writes to misa/minstret/mcycle [v1,22/22] RISC-V: Remove support for adhoc X_COP interrupt

Message ID

1520369790-38306-18-git-send-email-mjc@sifive.com

State

New

Headers

From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Date: Wed,  7 Mar 2018 09:56:27 +1300
Message-Id: <1520369790-38306-18-git-send-email-mjc@sifive.com>
In-Reply-To: <1520369790-38306-1-git-send-email-mjc@sifive.com>
References: <1520369790-38306-1-git-send-email-mjc@sifive.com>
Subject: [Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39
	and sv48
Precedence: list
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches <patches@groups.riscv.org>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

None | expand

Commit Message

Michael Clark March 6, 2018, 8:56 p.m. UTC

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7c4482b..f47fc9c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -24,8 +24,8 @@ 
 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
 #if defined(TARGET_RISCV64)
 #define TARGET_LONG_BITS 64
-#define TARGET_PHYS_ADDR_SPACE_BITS 50
-#define TARGET_VIRT_ADDR_SPACE_BITS 39
+#define TARGET_PHYS_ADDR_SPACE_BITS 52
+#define TARGET_VIRT_ADDR_SPACE_BITS 48
 #elif defined(TARGET_RISCV32)
 #define TARGET_LONG_BITS 32
 #define TARGET_PHYS_ADDR_SPACE_BITS 34