[v1,15/22] RISC-V: Use memory_region_is_ram in atomic pte

Message ID	1520369037-37977-16-git-send-email-mjc@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Michael Clark <mjc@sifive.com> To: qemu-devel@nongnu.org Date: Wed, 7 Mar 2018 09:43:50 +1300 Message-Id: <1520369037-37977-16-git-send-email-mjc@sifive.com> In-Reply-To: <1520369037-37977-1-git-send-email-mjc@sifive.com> References: <1520369037-37977-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v1 15/22] RISC-V: Use memory_region_is_ram in atomic pte Precedence: list Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches update <patches@groups.riscv.org> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	Spec conformance bug fixes and cleanups \| expand [v1,00/22] Spec conformance bug fixes and cleanups [v1,01/22] RISC-V: Make virt create_fdt interface consistent [v1,02/22] RISC-V: Replace hardcoded constants with enum values [v1,03/22] RISC-V: Make virt board description match spike [v1,04/22] RISC-V: Use ROM base address and size from memory [v1,05/22] RISC-V: Remove redundant identity_translate from [v1,06/22] RISC-V: Mark ROM read-only after copying in code and [v1,07/22] RISC-V: Remove unused class definitions from [v1,08/22] RISC-V: Make sure the emulated rom has space for [v1,09/22] RISC-V: Include hexidecimal instruction in [v1,10/22] RISC-V: Hold rcu_read_lock when accessing memory [v1,11/22] RISC-V: Improve page table walker spec compliance [v1,12/22] RISC-V: Update E order and I extension order [v1,13/22] RISC-V: Make spike and virt header guards more [v1,14/22] RISC-V: Make virt header comment title consistent [v1,15/22] RISC-V: Use memory_region_is_ram in atomic pte [v1,16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection from [v1,17/22] RISC-V: Ingore satp writes and return 0 for reads [v1,18/22] RISC-V: Remove braces from satp case statement with [v1,19/22] RISC-V: riscv-qemu port supports sv39 and sv48 [v1,20/22] RISC-V: vectored traps are optional

Message ID

1520369037-37977-16-git-send-email-mjc@sifive.com

State

New

Headers

From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Date: Wed,  7 Mar 2018 09:43:50 +1300
Message-Id: <1520369037-37977-16-git-send-email-mjc@sifive.com>
In-Reply-To: <1520369037-37977-1-git-send-email-mjc@sifive.com>
References: <1520369037-37977-1-git-send-email-mjc@sifive.com>
Subject: [Qemu-devel] [PATCH v1 15/22] RISC-V: Use memory_region_is_ram in
	atomic pte
Precedence: list
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches update <patches@groups.riscv.org>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

Spec conformance bug fixes and cleanups | expand

Commit Message

Michael Clark March 6, 2018, 8:43 p.m. UTC

After reading cpu_physical_memory_write and friends, it seems
that memory_region_is_ram is a more appropriate interface,
and matches the intent of the code that is calling it.

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index 2165ecb..88551be 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -235,7 +235,7 @@  restart:
                 rcu_read_lock();
                 mr = address_space_translate(cs->as, pte_addr,
                     &addr1, &l, false);
-                if (memory_access_is_direct(mr, true)) {
+                if (memory_region_is_ram(mr)) {
                     target_ulong *pte_pa =
                         qemu_map_ram_ptr(mr->ram_block, addr1);
 #if TCG_OVERSIZED_GUEST