From patchwork Thu Mar 24 12:27:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 88179 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CFE54B6F92 for ; Thu, 24 Mar 2011 23:29:35 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7001228102; Thu, 24 Mar 2011 13:29:11 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EE0mOhj-U3bO; Thu, 24 Mar 2011 13:29:11 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5C4F12812E; Thu, 24 Mar 2011 13:28:43 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C1B4528109 for ; Thu, 24 Mar 2011 13:28:39 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id K+Cic6EYS4zc for ; Thu, 24 Mar 2011 13:28:39 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from atcpcs01.andestech.com (unknown [118.99.208.106]) by theia.denx.de (Postfix) with ESMTP id B245228105 for ; Thu, 24 Mar 2011 13:28:29 +0100 (CET) Thread-Index: AcvqHvPIo7QKijgJSMuM0daI5rcgGg== Received: from ATCPCS06.andestech.com ([10.0.1.236]) by atcpcs01.andestech.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 24 Mar 2011 20:28:16 +0800 Received: from app01.andestech.com ([10.0.4.31]) by ATCPCS06.andestech.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 24 Mar 2011 20:28:16 +0800 From: "Macpaul Lin" To: , , , , Date: Thu, 24 Mar 2011 20:27:59 +0800 Message-ID: <1300969687-2428-5-git-send-email-macpaul@andestech.com> X-Mailer: git-send-email 1.7.3.5 In-Reply-To: <1300969687-2428-1-git-send-email-macpaul@andestech.com> References: <1300969687-2428-1-git-send-email-macpaul@andestech.com> X-MimeOLE: Produced By Microsoft MimeOLE V6.00.3790.4721 Content-class: urn:content-classes:message Importance: normal Priority: normal X-OriginalArrivalTime: 24 Mar 2011 12:28:16.0166 (UTC) FILETIME=[F3478460:01CBEA1E] Cc: Macpaul Lin Subject: [U-Boot] [PATCH v6 05/13] nds32/ag101: dev offset header of SoC ag101 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add header file of device offset support for SoC ag101. SoC ag101 is the first chip using NDS32 N1213 cpu core. Note: Ag101 is actually use ftsdmc021 instead of ftsdmc020 as dram controller, which is probably wrong in the datasheet. Signed-off-by: Macpaul Lin --- arch/nds32/include/asm/arch-ag101/ag101.h | 76 +++++++++++++++++++++++++++++ 1 files changed, 76 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h +#define CONFIG_FTUART010_02_BASE 0x99600000 /* ST UART ? SSP 02 (UART 02 in Linux) */ + +/* The following address was not defined in Linux */ +#define CONFIG_FTUART010_03_BASE 0x98200000 /* FF UART 3 */ +#define CONFIG_FTSSP010_01_BASE 0x98B00000 /* Synchronous Serial Port Controller (SSP) 01 */ +#define CONFIG_IRDA_BASE 0x98900000 /* IrDA */ +#define CONFIG_PMW_BASE 0x99100000 /* PWM - Pulse Width Modulator Controller */ + +#endif /* __AG101_H */ diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h new file mode 100644 index 0000000..a1d2d0a --- /dev/null +++ b/arch/nds32/include/asm/arch-ag101/ag101.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __AG101_H +#define __AG101_H + +/************************************************************************ + * Copyright AndesTech Corp 2005-2011. All rights reserved. * + *----------------------------------------------------------------------* + * Name: ag101.h * + * Description: ADP_AG101 SoC specfic define * + * Author: Nobuhiro Lin * + * Update: Macpaul Lin * + ************************************************************************/ + +/* Hardware register bases */ +#define CONFIG_FTAHBC020S_BASE 0x90100000 /* AHB Controller */ +#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller (SRAM) */ +#define CONFIG_FTSDMC021_BASE 0x90300000 /* FTSDMC020/021 SDRAM Controller */ +#define CONFIG_FTDMAC020_BASE 0x90400000 /* DMA Controller */ +#define CONFIG_FTAPBBRG020S_01_BASE 0x90500000 /* AHB-to-APB Bridge */ +#define CONFIG_FTLCDC100_BASE 0x90600000 /* LCD Controller */ +#define CONFIG_RESERVED_01_BASE 0x90700000 /* Reserved */ +#define CONFIG_RESERVED_02_BASE 0x90800000 /* Reserved */ +#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ +#define CONFIG_EXT_USB_HOST_BASE 0x90A00000 /* External USB host */ +#define CONFIG_USB_DEV_BASE 0x90B00000 /* USB Device */ +#define CONFIG_EXT_AHBPCIBRG_BASE 0x90C00000 /* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */ +#define CONFIG_RESERVED_03_BASE 0x90D00000 /* Reserved */ +#define CONFIG_EXT_AHBAPBBRG_BASE 0x90E00000 /* External AHB-to-APB Bridger (FTAPBBRG020S_02) */ +#define CONFIG_EXT_AHBSLAVE01_BASE 0x90F00000 /* External AHB slave1 (LCD) */ + +#define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000 /* External AHB slave2 (FUSBH200) */ + +/* DEBUG LED */ +#define CONFIG_DEBUG_LED 0x902FFFFC /* Debug LED */ + +/* APB Device definitions */ +#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ +#define CONFIG_FTUART010_01_BASE 0x98300000 /* BT UART 2/IrDA (UART 01 in Linux) */ +#define CONFIG_FTTMR010_BASE 0x98400000 /* Counter/Timers */ +#define CONFIG_FTWDT010_BASE 0x98500000 /* Watchdog Timer */ +#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock */ +#define CONFIG_FTGPIO010_BASE 0x98700000 /* GPIO */ +#define CONFIG_FTINTC010_BASE 0x98800000 /* Interrupt Controller */ +#define CONFIG_FTIIC010_BASE 0x98A00000 /* I2C */ +#define CONFIG_RESERVED_04_BASE 0x98C00000 /* Reserved */ +#define CONFIG_FTCFC010_BASE 0x98D00000 /* Compat Flash Controller */ +#define CONFIG_FTSDC010_BASE 0x98E00000 /* SD Controller */ + +#define CONFIG_FTSSP010_02_BASE 0x99400000 /* Synchronous Serial Port Controller (SSP) I2S/AC97 */