From patchwork Thu Mar 24 11:25:24 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 88169 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 77CD91007D2 for ; Thu, 24 Mar 2011 22:25:41 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 50080280EC; Thu, 24 Mar 2011 12:25:38 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GfVHBzznzLsj; Thu, 24 Mar 2011 12:25:37 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4DE1D280B7; Thu, 24 Mar 2011 12:25:36 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 04D27280B7 for ; Thu, 24 Mar 2011 12:25:34 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sjE8-iLxqVCo for ; Thu, 24 Mar 2011 12:25:32 +0100 (CET) X-Greylist: delayed 3781 seconds by postgrey-1.27 at theia; Thu, 24 Mar 2011 12:25:30 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from atcpcs01.andestech.com (unknown [118.99.208.106]) by theia.denx.de (Postfix) with ESMTP id 07370280B6 for ; Thu, 24 Mar 2011 12:25:30 +0100 (CET) Thread-Index: AcvqFi05nYgDjT9dRMmotpL27TBsiA== Received: from ATCPCS06.andestech.com ([10.0.1.236]) by atcpcs01.andestech.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 24 Mar 2011 19:25:27 +0800 Received: from app01.andestech.com ([10.0.4.31]) by ATCPCS06.andestech.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 24 Mar 2011 19:25:27 +0800 From: "Macpaul Lin" To: , , Date: Thu, 24 Mar 2011 19:25:24 +0800 Message-ID: <1300965924-20508-1-git-send-email-macpaul@andestech.com> X-Mailer: git-send-email 1.7.3.5 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.3790.4721 Content-class: urn:content-classes:message Importance: normal Priority: normal X-OriginalArrivalTime: 24 Mar 2011 11:25:27.0553 (UTC) FILETIME=[2D02CF10:01CBEA16] Cc: Macpaul Lin Subject: [U-Boot] [PATCH] ftsmc020: enhance for features and asm support. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de 1. Enhance ftsmc020 according to datasheets. 2. Add assembly register offsets for support lowlevel_init.S. Signed-off-by: Macpaul Lin --- Note: This patch should be applied after patch "[U-Boot,v2,4/4] ftsmc020: move ftsmc020 static mem controller to driver/mtd" (/patch/87862/) is applied. include/faraday/ftsmc020.h | 28 ++++++++++++++++++++++++++++ 1 files changed, 28 insertions(+), 0 deletions(-) diff --git a/include/faraday/ftsmc020.h b/include/faraday/ftsmc020.h index 95d9500..a980c1c 100644 --- a/include/faraday/ftsmc020.h +++ b/include/faraday/ftsmc020.h @@ -46,6 +46,10 @@ void ftsmc020_init(void); #define FTSMC020_BANK_WPROT (1 << 11) +#define FTSMC020_BANK_TYPE1 (1 << 10) +#define FTSMC020_BANK_TYPE2 (1 << 9) +#define FTSMC020_BANK_TYPE3 (1 << 8) + #define FTSMC020_BANK_SIZE_32K (0xb << 4) #define FTSMC020_BANK_SIZE_64K (0xc << 4) #define FTSMC020_BANK_SIZE_128K (0xd << 4) @@ -57,6 +61,7 @@ void ftsmc020_init(void); #define FTSMC020_BANK_SIZE_8M (0x3 << 4) #define FTSMC020_BANK_SIZE_16M (0x4 << 4) #define FTSMC020_BANK_SIZE_32M (0x5 << 4) +#define FTSMC020_BANK_SIZE_64M (0x6 << 4) #define FTSMC020_BANK_MBW_8 (0x0 << 0) #define FTSMC020_BANK_MBW_16 (0x1 << 0) @@ -76,4 +81,27 @@ void ftsmc020_init(void); #define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) #define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) +/* + * CONFIG and TIME Registers Offsets in ASSEMBLY + */ +#ifdef __ASSEMBLY__ +#define FTSMC020_CONFIG0 0x00 +#define FTSMC020_TIME0 0x04 +#define FTSMC020_CONFIG1 0x08 +#define FTSMC020_TIME1 0x0C +#define FTSMC020_CONFIG2 0x10 +#define FTSMC020_TIME2 0x14 +#define FTSMC020_CONFIG3 0x18 +#define FTSMC020_TIME3 0x1C +#define FTSMC020_CONFIG4 0x20 +#define FTSMC020_TIME4 0x24 +#define FTSMC020_CONFIG5 0x28 +#define FTSMC020_TIME5 0x2C +#define FTSMC020_CONFIG6 0x30 +#define FTSMC020_TIME6 0x34 +#define FTSMC020_CONFIG7 0x38 +#define FTSMC020_TIME7 0x3C +#define FTSMC020_SHADOW 0x40 +#endif /* __ASSEMBLY__ */ + #endif /* __FTSMC020_H */