From patchwork Wed Mar 23 02:17:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [v5,4/4] piix_pci: load path clean up Date: Tue, 22 Mar 2011 16:17:23 -0000 From: Isaku Yamahata X-Patchwork-Id: 87989 Message-Id: To: qemu-devel@nongnu.org Cc: yamahata@valinux.co.jp, mst@redhat.com The previous patch didn't change the behavior when load, it resulted in ugly code. This patch cleans it up. With this patch, pic irq lines are manipulated when loaded. It is expected that it won't change the behaviour because the interrupts are level: at the moment e.g. pci devices already reassert interrupts on load. Signed-off-by: Isaku Yamahata --- Changes v3 -> v4: - newly introduced - TODO: test more OSes, stress test with save/load, live-migration --- hw/piix_pci.c | 12 ++++-------- 1 files changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 11d069e..c019793 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -280,8 +280,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) ((PIIX_NUM_PIRQS - 1) << (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level, - bool propagate) +static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) { int pic_irq; uint64_t mask; @@ -295,15 +294,13 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level, piix3->pic_levels &= ~mask; piix3->pic_levels |= mask * !!level; - if (propagate) { - piix3_set_irq_pic(piix3, pic_irq); - } + piix3_set_irq_pic(piix3, pic_irq); } static void piix3_set_irq(void *opaque, int pirq, int level) { PIIX3State *piix3 = opaque; - piix3_set_irq_level(piix3, pirq, level, true); + piix3_set_irq_level(piix3, pirq, level); } /* irq routing is changed. so rebuild bitmap */ @@ -314,8 +311,7 @@ static void piix3_update_irq_levels(PIIX3State *piix3) piix3->pic_levels = 0; for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { piix3_set_irq_level(piix3, pirq, - pci_bus_get_irq_level(piix3->dev.bus, pirq), - false); + pci_bus_get_irq_level(piix3->dev.bus, pirq)); } }