From patchwork Tue Mar 22 20:40:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Rigby X-Patchwork-Id: 87960 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 823EDB6F0B for ; Wed, 23 Mar 2011 07:48:33 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D9914280A8; Tue, 22 Mar 2011 21:48:31 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id efCKmNIWaON0; Tue, 22 Mar 2011 21:48:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3D3BA2809D; Tue, 22 Mar 2011 21:48:28 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 20E1D2809D for ; Tue, 22 Mar 2011 21:48:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id h5LkFEe7sQXq for ; Tue, 22 Mar 2011 21:48:25 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pw0-f44.google.com (mail-pw0-f44.google.com [209.85.160.44]) by theia.denx.de (Postfix) with ESMTPS id 06D7A28099 for ; Tue, 22 Mar 2011 21:48:22 +0100 (CET) Received: by pwi5 with SMTP id 5so962944pwi.3 for ; Tue, 22 Mar 2011 13:48:21 -0700 (PDT) Received: by 10.142.12.16 with SMTP id 16mr4525511wfl.253.1300826451264; Tue, 22 Mar 2011 13:40:51 -0700 (PDT) Received: from localhost.localdomain (c-76-23-54-220.hsd1.ut.comcast.net [76.23.54.220]) by mx.google.com with ESMTPS id n4sm9096243wfl.2.2011.03.22.13.40.47 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Mar 2011 13:40:50 -0700 (PDT) From: John Rigby To: u-boot@lists.denx.de Date: Tue, 22 Mar 2011 14:40:16 -0600 Message-Id: <1300826419-18632-2-git-send-email-john.rigby@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1300826419-18632-1-git-send-email-john.rigby@linaro.org> References: <1300826419-18632-1-git-send-email-john.rigby@linaro.org> Cc: Rabin Vincent , patches@linaro.org Subject: [U-Boot] [PATCH 1/4] p101x: extra init for u8500 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Rabin Vincent empty fifo on init program receive line control register on u8500 Signed-off-by: Rabin Vincent --- drivers/serial/serial_pl01x.c | 10 ++++++++++ drivers/serial/serial_pl01x.h | 4 ++++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 5dfcde8..22ada8f 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -112,6 +112,12 @@ int serial_init (void) unsigned int remainder; unsigned int fraction; + /* Empty RX fifo if necessary */ + if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { + while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) + readl(®s->dr); + } + /* First, disable everything */ writel(0, ®s->pl011_cr); @@ -134,6 +140,10 @@ int serial_init (void) writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN, ®s->pl011_lcrh); +#ifdef CONFIG_U8500 + /* program receive line control register */ + writel(0x70, ®s->pl011_rlcr); +#endif /* Finally, enable the UART */ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE, ®s->pl011_cr); diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h index b670c24..fdd3911 100644 --- a/drivers/serial/serial_pl01x.h +++ b/drivers/serial/serial_pl01x.h @@ -43,7 +43,11 @@ struct pl01x_regs { u32 pl010_lcrl; /* 0x10 Line control register, low byte */ u32 pl010_cr; /* 0x14 Control register */ u32 fr; /* 0x18 Flag register (Read only) */ +#ifdef CONFIG_U8500 + u32 pl011_rlcr; /* 0x1c Receive line control register */ +#else u32 reserved; +#endif u32 ilpr; /* 0x20 IrDA low-power counter register */ u32 pl011_ibrd; /* 0x24 Integer baud rate register */ u32 pl011_fbrd; /* 0x28 Fractional baud rate register */