Patchwork [U-Boot,1/4] p101x: extra init for u8500

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Submitter John Rigby
Date March 22, 2011, 8:40 p.m.
Message ID <1300826419-18632-2-git-send-email-john.rigby@linaro.org>
Download mbox | patch
Permalink /patch/87960/
State Changes Requested
Headers show

Comments

John Rigby - March 22, 2011, 8:40 p.m.
From: Rabin Vincent <rabin.vincent@stericsson.com>

empty fifo on init
program receive line control register on u8500

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
---
 drivers/serial/serial_pl01x.c |   10 ++++++++++
 drivers/serial/serial_pl01x.h |    4 ++++
 2 files changed, 14 insertions(+), 0 deletions(-)

Patch

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 5dfcde8..22ada8f 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -112,6 +112,12 @@  int serial_init (void)
 	unsigned int remainder;
 	unsigned int fraction;
 
+	/* Empty RX fifo if necessary */
+	if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
+		while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
+			readl(&regs->dr);
+	}
+
 	/* First, disable everything */
 	writel(0, &regs->pl011_cr);
 
@@ -134,6 +140,10 @@  int serial_init (void)
 	writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN,
 	       &regs->pl011_lcrh);
 
+#ifdef CONFIG_U8500
+	/* program receive line control register */
+	writel(0x70, &regs->pl011_rlcr);
+#endif
 	/* Finally, enable the UART */
 	writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
 	       &regs->pl011_cr);
diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h
index b670c24..fdd3911 100644
--- a/drivers/serial/serial_pl01x.h
+++ b/drivers/serial/serial_pl01x.h
@@ -43,7 +43,11 @@  struct pl01x_regs {
 	u32	pl010_lcrl;	/* 0x10 Line control register, low byte */
 	u32	pl010_cr;	/* 0x14 Control register */
 	u32	fr;		/* 0x18 Flag register (Read only) */
+#ifdef CONFIG_U8500
+	u32	pl011_rlcr;	/* 0x1c Receive line control register */
+#else
 	u32	reserved;
+#endif
 	u32	ilpr;		/* 0x20 IrDA low-power counter register */
 	u32	pl011_ibrd;	/* 0x24 Integer baud rate register */
 	u32	pl011_fbrd;	/* 0x28 Fractional baud rate register */