From patchwork Wed Feb 28 18:14:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: 'Manivannan Sadhasivam' X-Patchwork-Id: 879283 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="NKIJ303a"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zs3gW0ydgz9s2Z for ; Thu, 1 Mar 2018 05:17:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932671AbeB1SQX (ORCPT ); Wed, 28 Feb 2018 13:16:23 -0500 Received: from mail-pl0-f65.google.com ([209.85.160.65]:33319 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932670AbeB1SQS (ORCPT ); Wed, 28 Feb 2018 13:16:18 -0500 Received: by mail-pl0-f65.google.com with SMTP id c11-v6so2005035plo.0 for ; Wed, 28 Feb 2018 10:16:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wQ9V5E+5Q215PiZbuRn9/CeJqGXim6lmXzqmFDef8pg=; b=NKIJ303awy0T+/OJ59A1+wa9b5krhgR7ZaDJ7bolBpPfapHisumyVTlNz0QSMFJeIj geM4a5IIvDlw8UZdmHbg4MDidgJid3NTLL40AS9sS7VBpw8PeOuP6HcQSMyHDzUAswmn QYBMerIAKgv7nK+zE3fNdMp8ChjFWu7f24YoM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wQ9V5E+5Q215PiZbuRn9/CeJqGXim6lmXzqmFDef8pg=; b=lkQqCL8e2yiU6S09MDjbaPanw7o5hDZQ4meaJW5Ey5Ir9qJoa6lmBbTdVwhiaVoCYV rBqJmenKg3Hj9wHcK9YLESgAlv+XKYemCo9PnnbOkHsZwPqZOtr+bgJZRyOqxEEa9aDQ 0CURJQbHPl2idD5LT8ZbKjNVGcOm29pgbVNunQQ6slDmaILFMI8MNOUIzEobHie8K9fX SFZ4E4H8oFBCo1x+trrFArfeHn79YeVhX7HCPj31WB/29Z/pv4sKQQ525CUBEA6Pbvdf gZyOS88SrSVjGbzPiQa/cMjvm/hrmpSHYyiIH7jt091dDhqUY4NtgPT21+9qcfakjJN+ 1fgQ== X-Gm-Message-State: APf1xPDQHM6AA+YDp0uqUdvTcyoVJFrIO0ebIQXYW2l3/ShjGbGPGNW9 dvDPDmiMDfiKaWhNHqfi/fvh X-Google-Smtp-Source: AG47ELuHrMTnu3u/5dpUXyctEoFWvjaWDTDuv93p+xvkj9hzoTorPvCo9WwSuvbeXnxu+MqEVZFoLA== X-Received: by 2002:a17:902:b187:: with SMTP id s7-v6mr1561673plr.448.1519841777383; Wed, 28 Feb 2018 10:16:17 -0800 (PST) Received: from localhost.localdomain ([2405:204:7380:867e:a4dd:d27b:1244:f453]) by smtp.gmail.com with ESMTPSA id u27sm4980258pfk.172.2018.02.28.10.16.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 10:16:16 -0800 (PST) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v3 08/10] gpio: Add gpio driver for Actions OWL S900 SoC Date: Wed, 28 Feb 2018 23:44:30 +0530 Message-Id: <20180228181432.26847-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180228181432.26847-1-manivannan.sadhasivam@linaro.org> References: <20180228181432.26847-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add gpio driver for Actions Semi OWL family S900 SoC. Set of registers controlling the gpio shares the same register range with pinctrl block. GPIO registers are organized as 6 banks and each bank controls the maximum of 32 gpios. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andy Shevchenko --- drivers/gpio/Kconfig | 8 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-owl.c | 218 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+) create mode 100644 drivers/gpio/gpio-owl.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8dbb2280538d..09ceb98e2434 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -364,6 +364,14 @@ config GPIO_OMAP help Say yes here to enable GPIO support for TI OMAP SoCs. +config GPIO_OWL + tristate "Actions OWL GPIO support" + default ARCH_ACTIONS + depends on ARCH_ACTIONS || COMPILE_TEST + depends on OF_GPIO + help + Say yes here to enable GPIO support for Actions OWL SoCs. + config GPIO_PL061 bool "PrimeCell PL061 GPIO support" depends on ARM_AMBA diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index cccb0d40846c..b2bb11d4675f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -91,6 +91,7 @@ obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o obj-$(CONFIG_GPIO_OMAP) += gpio-omap.o +obj-$(CONFIG_GPIO_OWL) += gpio-owl.o obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o obj-$(CONFIG_GPIO_PCH) += gpio-pch.o diff --git a/drivers/gpio/gpio-owl.c b/drivers/gpio/gpio-owl.c new file mode 100644 index 000000000000..98f2e98197bc --- /dev/null +++ b/drivers/gpio/gpio-owl.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OWL SoC's GPIO driver + * + * Copyright (c) 2018 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_OUTEN 0x0000 +#define GPIO_INEN 0x0004 +#define GPIO_DAT 0x0008 + +#define OWL_GPIO_PORT_A 0 +#define OWL_GPIO_PORT_B 1 +#define OWL_GPIO_PORT_C 2 +#define OWL_GPIO_PORT_D 3 +#define OWL_GPIO_PORT_E 4 +#define OWL_GPIO_PORT_F 5 + +struct owl_gpio_port { + const char *name; + unsigned int offset; + unsigned int pins; +}; + +struct owl_gpio { + struct gpio_chip gpio; + const struct owl_gpio_port *port; + void __iomem *base; + int id; +}; + +static void owl_gpio_set_reg(void __iomem *base, unsigned int pin, int flag) +{ + u32 val; + + val = readl_relaxed(base); + + if (flag) + val |= BIT(pin); + else + val &= ~BIT(pin); + + writel_relaxed(val, base); +} + +static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + + /* + * GPIOs have higher priority over other modules, so either setting + * them as OUT or IN is sufficient + */ + owl_gpio_set_reg(gpio_base + GPIO_OUTEN, offset, true); + + return 0; +} + +static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + + /* disable gpio output */ + owl_gpio_set_reg(gpio_base + GPIO_OUTEN, offset, false); + + /* disable gpio input */ + owl_gpio_set_reg(gpio_base + GPIO_INEN, offset, false); +} + +static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + u32 val; + + val = readl_relaxed(gpio_base + GPIO_DAT); + + return !!(val & BIT(offset)); +} + +static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + u32 val; + + val = readl_relaxed(gpio_base + GPIO_DAT); + + if (value) + val |= BIT(offset); + else + val &= ~BIT(offset); + + writel_relaxed(val, gpio_base + GPIO_DAT); +} + +static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + + owl_gpio_set_reg(gpio_base + GPIO_OUTEN, offset, false); + owl_gpio_set_reg(gpio_base + GPIO_INEN, offset, true); + + return 0; +} + +static int owl_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct owl_gpio *gpio = gpiochip_get_data(chip); + const struct owl_gpio_port *port = gpio->port; + void __iomem *gpio_base = gpio->base + port->offset; + + owl_gpio_set_reg(gpio_base + GPIO_INEN, offset, false); + owl_gpio_set_reg(gpio_base + GPIO_OUTEN, offset, true); + owl_gpio_set(chip, offset, value); + + return 0; +} + +#define OWL_GPIO_PORT(port, base, count) \ + [OWL_GPIO_PORT_##port] = { \ + .name = #port, \ + .offset = base, \ + .pins = count, \ + } + +static const struct owl_gpio_port s900_gpio_ports[] = { + OWL_GPIO_PORT(A, 0x0000, 32), + OWL_GPIO_PORT(B, 0x000C, 32), + OWL_GPIO_PORT(C, 0x0018, 12), + OWL_GPIO_PORT(D, 0x0024, 30), + OWL_GPIO_PORT(E, 0x0030, 32), + OWL_GPIO_PORT(F, 0x00F0, 8), +}; + +static int owl_gpio_probe(struct platform_device *pdev) +{ + struct owl_gpio *gpio; + const struct owl_gpio_port *port; + int ret; + + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) + return -ENOMEM; + + gpio->base = of_iomap(pdev->dev.of_node, 0); + if (IS_ERR(gpio->base)) + return PTR_ERR(gpio->base); + + gpio->id = of_alias_get_id(pdev->dev.of_node, "gpio"); + if (gpio->id < 0) + return gpio->id; + + port = &s900_gpio_ports[gpio->id]; + + gpio->gpio.request = owl_gpio_request; + gpio->gpio.free = owl_gpio_free; + gpio->gpio.get = owl_gpio_get; + gpio->gpio.set = owl_gpio_set; + gpio->gpio.direction_input = owl_gpio_direction_input; + gpio->gpio.direction_output = owl_gpio_direction_output; + + gpio->gpio.base = -1; + gpio->gpio.parent = &pdev->dev; + gpio->gpio.label = port->name; + gpio->gpio.ngpio = port->pins; + + gpio->port = port; + + platform_set_drvdata(pdev, gpio); + + ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register gpiochip\n"); + return ret; + } + + return 0; +} + +static const struct of_device_id owl_gpio_of_match[] = { + { .compatible = "actions,s900-gpio", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, owl_gpio_of_match); + +static struct platform_driver owl_gpio_driver = { + .driver = { + .name = "owl-gpio", + .of_match_table = owl_gpio_of_match, + }, + .probe = owl_gpio_probe, +}; +module_platform_driver(owl_gpio_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Actions Semi OWL SoCs GPIO driver"); +MODULE_LICENSE("GPL");