From patchwork Tue Feb 27 17:52:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 878733 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="E2Fxr7OL"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zrRMr4vdFz9s4V for ; Wed, 28 Feb 2018 05:01:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751721AbeB0SB0 (ORCPT ); Tue, 27 Feb 2018 13:01:26 -0500 Received: from mail-pg0-f67.google.com ([74.125.83.67]:37176 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751756AbeB0SBY (ORCPT ); Tue, 27 Feb 2018 13:01:24 -0500 Received: by mail-pg0-f67.google.com with SMTP id y26so7808067pgv.4; Tue, 27 Feb 2018 10:01:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bwRgD2Eh4ib4PFpj6mjM4J5wk5v8ULM2kiBmc0RQj5o=; b=E2Fxr7OLcz6Rp6grrM5ikajDq7pvwz+xiNokWM+KyE0AdsnW+nhsnL329P/rXo6RZk GfMzgfMm3MRm4KBcGfoRZD14H+7kJXZe1awfywH7R79M3gqf0q7866KzA9zHFfpa7RHS B+EGRox98gi4wAk4IeT07sTMw8jsnvAq01XeF4VeETSDxKmrKOZf9h4t9DDc6S3WSYYK rvjTSJi8lB4wAjFWns6f3t8zi+QsWK6ucJNQZE+p9azT28BXlHbdYWMecVbiaBcg8Has F6U9cj/JjR7hCdPKQtWnQj7iSSudPFuGSzaYG5UXlrJtj4A6POyXUhiDPnZynAdFYLZd YKhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bwRgD2Eh4ib4PFpj6mjM4J5wk5v8ULM2kiBmc0RQj5o=; b=Hmdj2NpDDQEHW1sAjIdAYEE8Si5xSAi6nuSadCLVZaQUcdKqbzMnui5yVU4EfX0KoY IRiPQUCRbQ2NbmScLWOjmDvLw4P7TbJYCsyhhTGsVCFdMeciPD+TFytMgZ/UaIrvFx/N qYVQuQbmOOm/Q/24ma5qC1RMWlKB7ce3JhDZXuiZR1QQ8LBkgSlwi7tBkzylUMHqg8uS f+h1rh/k7c+6P5p/VW5GGnVtMEotNXPBsRCG9g969OzWKmZI1cZpdUyoqN/50T+eee6X yb84yY0SYIw2C/8EaYcjxbZbpOxNGc5oztD3TzFh42xRHvmJeylVIUaMqXeq2z/V+WRs jjvQ== X-Gm-Message-State: APf1xPAa3LrsFhJOmmxg1EZr0fVuMt0gHmvMIbxiK00NMs7LxIFM+RyT XIGb5htUIqH+XHPtSn96VBE= X-Google-Smtp-Source: AH8x2246Y7Ri9rpHJgeOeuoDC85u5tLZZmkyELcDS/xkZ8vW1XcXpTmBmM/34QswwoZE7XURxNBBkg== X-Received: by 10.99.179.77 with SMTP id x13mr12040930pgt.148.1519754483035; Tue, 27 Feb 2018 10:01:23 -0800 (PST) Received: from simonLocalRHEL7.x64 ([101.80.181.226]) by smtp.gmail.com with ESMTPSA id m83sm24360910pfk.107.2018.02.27.10.01.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 10:01:22 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH v2 18/30] KVM: PPC: Book3S PR: always fail transaction in guest privilege state Date: Wed, 28 Feb 2018 01:52:26 +0800 Message-Id: <1519753958-11756-8-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1519753958-11756-1-git-send-email-wei.guo.simon@gmail.com> References: <1519753958-11756-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo Currently kernel doesn't use transaction memory. And there is an issue for privilege guest that: tbegin/tsuspend/tresume/tabort TM instructions can impact MSR TM bits without trap into PR host. So following code will lead to a false mfmsr result: tbegin <- MSR bits update to Transaction active. beq <- failover handler branch mfmsr <- still read MSR bits from magic page with transaction inactive. It is not an issue for non-privilege guest since its mfmsr is not patched with magic page and will always trap into PR host. This patch will always fail tbegin attempt for privilege guest, so that the above issue is prevented. It is benign since currently (guest) kernel doesn't initiate a transaction. Test case: https://github.com/justdoitqd/publicFiles/blob/master/test_tbegin_pr.c Signed-off-by: Simon Guo --- arch/powerpc/include/asm/kvm_book3s.h | 2 ++ arch/powerpc/kvm/book3s_emulate.c | 43 +++++++++++++++++++++++++++++++++++ arch/powerpc/kvm/book3s_pr.c | 11 ++++++++- 3 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index 2ecb6a3..9690280 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -258,9 +258,11 @@ extern void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu, #ifdef CONFIG_PPC_TRANSACTIONAL_MEM void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu); void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu); +void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu); #else static inline void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) {} static inline void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) {} +static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) {} #endif extern int kvm_irq_bypass; diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index a03533d..90b5f59 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "book3s.h" #define OP_19_XOP_RFID 18 @@ -47,6 +48,8 @@ #define OP_31_XOP_EIOIO 854 #define OP_31_XOP_SLBMFEE 915 +#define OP_31_XOP_TBEGIN 654 + /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */ #define OP_31_XOP_DCBZ 1010 @@ -362,6 +365,46 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, break; } +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + case OP_31_XOP_TBEGIN: + { + if (!cpu_has_feature(CPU_FTR_TM)) + break; + + if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { + kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG); + emulated = EMULATE_AGAIN; + break; + } + + if (!(kvmppc_get_msr(vcpu) & MSR_PR)) { + preempt_disable(); + vcpu->arch.cr = (CR0_TBEGIN_FAILURE | + (vcpu->arch.cr & ~(CR0_MASK << CR0_SHIFT))); + + vcpu->arch.texasr = (TEXASR_FS | TEXASR_EX | + (((u64)(TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) + << TEXASR_FC_LG)); + + if ((inst >> 21) & 0x1) + vcpu->arch.texasr |= TEXASR_ROT; + + if (kvmppc_get_msr(vcpu) & MSR_PR) + vcpu->arch.texasr |= TEXASR_PR; + + if (kvmppc_get_msr(vcpu) & MSR_HV) + vcpu->arch.texasr |= TEXASR_HV; + + vcpu->arch.tfhar = kvmppc_get_pc(vcpu) + 4; + vcpu->arch.tfiar = kvmppc_get_pc(vcpu); + + kvmppc_restore_tm_sprs(vcpu); + preempt_enable(); + } else + emulated = EMULATE_FAIL; + break; + } +#endif default: emulated = EMULATE_FAIL; } diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index 473c819..82e1a74 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -204,6 +204,15 @@ static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) #ifdef CONFIG_PPC_BOOK3S_64 smsr |= MSR_ISF | MSR_HV; #endif +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + /* + * in guest privileged state, we want to fail all TM transactions. + * So disable MSR TM bit so that all tbegin. will be able to be + * trapped into host. + */ + if (!(guest_msr & MSR_PR)) + smsr &= ~MSR_TM; +#endif vcpu->arch.shadow_msr = smsr; } @@ -301,7 +310,7 @@ static inline void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) tm_disable(); } -static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) +void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) { tm_enable(); mtspr(SPRN_TFHAR, vcpu->arch.tfhar);