From patchwork Tue Feb 27 17:52:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 878731 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="C2plwVs6"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zrRMh3DQkz9s32 for ; Wed, 28 Feb 2018 05:01:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751733AbeB0SBT (ORCPT ); Tue, 27 Feb 2018 13:01:19 -0500 Received: from mail-pf0-f196.google.com ([209.85.192.196]:40561 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751676AbeB0SBR (ORCPT ); Tue, 27 Feb 2018 13:01:17 -0500 Received: by mail-pf0-f196.google.com with SMTP id m5so8263843pff.7; Tue, 27 Feb 2018 10:01:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Hxts0Pg91H1aOyzn8+PJuvRZihbfSwsGmuf4lQv2PRM=; b=C2plwVs64MTn2JUPGyjVScTuaOsJlZIHxYVVWePX/DgK9oByGRewVh8r7je3Sk3GdW zBnXi5StoxzSJqkZKDBKpzXKkyw4MuruSp4qYGciON8aKn7VFCrY+17d17jJVWvb2k5J vW6XlwsDNaBBO3ksnzUlW52hcqRFVG7v+zgYaqW448I3xGzFaOkZKXScUyBuFu8lzeq5 mRUeabIEtDKoEQ7VM4yEkBZSfVQbS94olw6QqwxbfPfS2QaX5w14RDxTBAUI1GEj4Rt0 8CWJVS8y3hZaQ2xzMggSxkkoLbB15v1DxMd/nQNUFsPmFjDkcU7FtpRacv/ghhAtXKCP GoPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Hxts0Pg91H1aOyzn8+PJuvRZihbfSwsGmuf4lQv2PRM=; b=edM5Q3P3P4FHACy6Muj4qLafYEJ+yS58puhV/VBBKWjkiVlLmAgabjx6IY3fwFGplN Mqgrr8TT+643G7eNwlZlPHzGQWHoxrPNI8fCzHtwkHHn8Z2VXJngEtDSLCtD6MhKxS8t gvheDDrdvcvM4pb5hJTd+LGE752FYhhHtpMDcyUJ/oxu7kaocwHuDw1Oc4ifrkQYuc8q 3tZGk5T9MFqkbtEPsITLzcowPdvivCdewAApi/lUdInMfA2ezGNvUDUGT/td1ahKl9k0 bZs/QWl2cdYDUrjf118zCqXsUFoJqLOabWFNPa8/YPIfx6f5eYZBXjjrmnfIzHjaTGhz KAHQ== X-Gm-Message-State: APf1xPCBSD0CWJjpaXtu6tS27IpO3/XIn5DUYaryloAFfqbGtL6UEQOB QxcEZ8sdPbEavX7frk8BZ+w= X-Google-Smtp-Source: AH8x226NQIHUMYgYEVDsnlguLU3zlkrsY9VO6qH5byE6GWOoh9fRMwfBZCie5EJhPOhULnF8lHLjQQ== X-Received: by 10.98.110.71 with SMTP id j68mr13087965pfc.93.1519754476168; Tue, 27 Feb 2018 10:01:16 -0800 (PST) Received: from simonLocalRHEL7.x64 ([101.80.181.226]) by smtp.gmail.com with ESMTPSA id m83sm24360910pfk.107.2018.02.27.10.01.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 10:01:15 -0800 (PST) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Simon Guo Subject: [PATCH v2 15/30] KVM: PPC: Book3S PR: add transaction memory save/restore skeleton for PR KVM Date: Wed, 28 Feb 2018 01:52:23 +0800 Message-Id: <1519753958-11756-5-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1519753958-11756-1-git-send-email-wei.guo.simon@gmail.com> References: <1519753958-11756-1-git-send-email-wei.guo.simon@gmail.com> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Simon Guo The transaction memory checkpoint area save/restore behavior is triggered when VCPU qemu process is switching out/into CPU. ie. at kvmppc_core_vcpu_put_pr() and kvmppc_core_vcpu_load_pr(). MSR TM active state is determined by TS bits: active: 10(transactional) or 01 (suspended) inactive: 00 (non-transactional) We don't "fake" TM functionality for guest. We "sync" guest virtual MSR TM active state(10 or 01) with shadow MSR. That is to say, we don't emulate a transactional guest with a TM inactive MSR. TM SPR support(TFIAR/TFAR/TEXASR) has already been supported by commit 9916d57e64a4 ("KVM: PPC: Book3S PR: Expose TM registers"). Math register support (FPR/VMX/VSX) will be done at subsequent patch. Whether TM context need to be saved/restored can be determined by kvmppc_get_msr() TM active state: * TM active - save/restore TM context * TM inactive - no need to do so and only save/restore TM SPRs. Signed-off-by: Simon Guo Suggested-by: Paul Mackerras --- arch/powerpc/include/asm/kvm_book3s.h | 9 +++++++++ arch/powerpc/include/asm/kvm_host.h | 1 - arch/powerpc/kvm/book3s_pr.c | 27 +++++++++++++++++++++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index 9a66700..5911c3b 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -253,6 +253,15 @@ extern void kvmppc_copy_to_svcpu(struct kvmppc_book3s_shadow_vcpu *svcpu, struct kvm_vcpu *vcpu); extern void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu, struct kvmppc_book3s_shadow_vcpu *svcpu); + +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu); +void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu); +#else +static inline void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) {} +static inline void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) {} +#endif + extern int kvm_irq_bypass; static inline struct kvmppc_vcpu_book3s *to_book3s(struct kvm_vcpu *vcpu) diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h index fef8133..89b3fed 100644 --- a/arch/powerpc/include/asm/kvm_host.h +++ b/arch/powerpc/include/asm/kvm_host.h @@ -626,7 +626,6 @@ struct kvm_vcpu_arch { struct thread_vr_state vr_tm; u32 vrsave_tm; /* also USPRG0 */ - #endif #ifdef CONFIG_KVM_EXIT_TIMING diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index 91d0e59..ac9d58f 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -43,6 +43,7 @@ #include #include #include +#include #include "book3s.h" @@ -115,6 +116,8 @@ static void kvmppc_core_vcpu_load_pr(struct kvm_vcpu *vcpu, int cpu) if (kvmppc_is_split_real(vcpu)) kvmppc_fixup_split_real(vcpu); + + kvmppc_restore_tm_pr(vcpu); } static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu) @@ -134,6 +137,7 @@ static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu) kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); + kvmppc_save_tm_pr(vcpu); /* Enable AIL if supported */ if (cpu_has_feature(CPU_FTR_HVMODE) && @@ -306,6 +310,29 @@ static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) tm_disable(); } +void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) +{ + if (!(MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)))) { + kvmppc_save_tm_sprs(vcpu); + return; + } + + preempt_disable(); + _kvmppc_save_tm_pr(vcpu, mfmsr()); + preempt_enable(); +} + +void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) +{ + if (!MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) { + kvmppc_restore_tm_sprs(vcpu); + return; + } + + preempt_disable(); + _kvmppc_restore_tm_pr(vcpu, kvmppc_get_msr(vcpu)); + preempt_enable(); +} #endif static int kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu)